1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <cortex_a53.h> 35#include <cortex_a72.h> 36#include <plat_private.h> 37#include <platform_def.h> 38 39 .globl cpuson_entry_point 40 .globl cpuson_flags 41 .globl platform_cpu_warmboot 42 .globl plat_secondary_cold_boot_setup 43 .globl plat_report_exception 44 .globl platform_is_primary_cpu 45 .globl plat_crash_console_init 46 .globl plat_crash_console_putc 47 .globl plat_my_core_pos 48 .globl plat_reset_handler 49 50 51#define RK_REVISION(rev) RK_PLAT_CFG##rev 52#define RK_HANDLER(rev) plat_reset_handler_juno_r##rev 53#define JUMP_TO_HANDLER_IF_RK_R(revision) \ 54 jump_to_handler RK_REVISION(revision), RK_HANDLER(revision) 55 56 /* 57 * Helper macro to jump to the given handler if the board revision 58 * matches. 59 * Expects the Juno board revision in x0. 60 * 61 */ 62 .macro jump_to_handler _revision, _handler 63 cmp x0, #\_revision 64 b.eq \_handler 65 .endm 66 67 /* 68 * Helper macro that reads the part number of the current CPU and jumps 69 * to the given label if it matches the CPU MIDR provided. 70 */ 71 .macro jump_if_cpu_midr _cpu_midr, _label 72 mrs x0, midr_el1 73 ubfx x0, x0, MIDR_PN_SHIFT, #12 74 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 75 b.eq \_label 76 .endm 77 78 /* 79 * Platform reset handler for rockchip. 80 * only A53 cores 81 */ 82func RK_HANDLER(0) 83 ret 84endfunc RK_HANDLER(0) 85 86 /* 87 * Platform reset handler for rockchip. 88 * - Cortex-A53 processor cluster; 89 * - Cortex-A72 processor cluster. 90 * 91 * This handler does the following: 92 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 93 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 94 */ 95func RK_HANDLER(1) 96 /* 97 * Nothing to do on Cortex-A53. 98 * 99 */ 100 jump_if_cpu_midr CORTEX_A72_MIDR, A72 101 ret 102 103A72: 104 /* Cortex-A72 specific settings */ 105 mov x0, #((2 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 106 (0x1 << 5)) 107 msr L2CTLR_EL1, x0 108 isb 109 ret 110endfunc RK_HANDLER(1) 111 112 /* 113 * void plat_reset_handler(void); 114 * 115 * Determine the SOC type and call the appropriate reset 116 * handler. 117 * 118 */ 119func plat_reset_handler 120 121 mov x0, RK_PLAT_AARCH_CFG 122 123 JUMP_TO_HANDLER_IF_RK_R(0) 124 JUMP_TO_HANDLER_IF_RK_R(1) 125 126 /* SOC type is not supported */ 127not_supported: 128 b not_supported 129endfunc plat_reset_handler 130 131func plat_my_core_pos 132 mrs x0, mpidr_el1 133 and x1, x0, #MPIDR_CPU_MASK 134 and x0, x0, #MPIDR_CLUSTER_MASK 135 add x0, x1, x0, LSR #6 136 ret 137endfunc plat_my_core_pos 138 139 /* -------------------------------------------------------------------- 140 * void plat_secondary_cold_boot_setup (void); 141 * 142 * This function performs any platform specific actions 143 * needed for a secondary cpu after a cold reset e.g 144 * mark the cpu's presence, mechanism to place it in a 145 * holding pen etc. 146 * -------------------------------------------------------------------- 147 */ 148func plat_secondary_cold_boot_setup 149 /* rk3368 does not do cold boot for secondary CPU */ 150cb_panic: 151 b cb_panic 152endfunc plat_secondary_cold_boot_setup 153 154func platform_is_primary_cpu 155 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 156 cmp x0, #PLAT_RK_PRIMARY_CPU 157 cset x0, eq 158 ret 159endfunc platform_is_primary_cpu 160 161 /* -------------------------------------------------------------------- 162 * int plat_crash_console_init(void) 163 * Function to initialize the crash console 164 * without a C Runtime to print crash report. 165 * Clobber list : x0, x1, x2 166 * -------------------------------------------------------------------- 167 */ 168func plat_crash_console_init 169 mov_imm x0, PLAT_RK_UART_BASE 170 mov_imm x1, PLAT_RK_UART_CLOCK 171 mov_imm x2, PLAT_RK_UART_BAUDRATE 172 b console_core_init 173endfunc plat_crash_console_init 174 175 /* -------------------------------------------------------------------- 176 * int plat_crash_console_putc(void) 177 * Function to print a character on the crash 178 * console without a C Runtime. 179 * Clobber list : x1, x2 180 * -------------------------------------------------------------------- 181 */ 182func plat_crash_console_putc 183 mov_imm x1, PLAT_RK_UART_BASE 184 b console_core_putc 185endfunc plat_crash_console_putc 186 187 /* -------------------------------------------------------------------- 188 * void platform_cpu_warmboot (void); 189 * cpus online or resume enterpoint 190 * -------------------------------------------------------------------- 191 */ 192 .align 16 193func platform_cpu_warmboot 194 mrs x0, MPIDR_EL1 195 and x1, x0, #MPIDR_CPU_MASK 196 and x0, x0, #MPIDR_CLUSTER_MASK 197 /* -------------------------------------------------------------------- 198 * big cluster id is 1 199 * big cores id is from 0-3, little cores id 4-7 200 * -------------------------------------------------------------------- 201 */ 202 add x0, x1, x0, lsr #6 203 /* -------------------------------------------------------------------- 204 * get per cpuup flag 205 * -------------------------------------------------------------------- 206 */ 207 adr x4, cpuson_flags 208 add x4, x4, x0, lsl #2 209 ldr w1, [x4] 210 /* -------------------------------------------------------------------- 211 * check cpuon reason 212 * -------------------------------------------------------------------- 213 */ 214 ldr w3, =PMU_CPU_AUTO_PWRDN 215 cmp w1, w3 216 b.eq boot_entry 217 ldr w3, =PMU_CPU_HOTPLUG 218 cmp w1, w3 219 b.eq boot_entry 220 /* -------------------------------------------------------------------- 221 * If the boot core cpuson_flags or cpuson_entry_point is not 222 * expection. force the core into wfe. 223 * -------------------------------------------------------------------- 224 */ 225wfe_loop: 226 wfe 227 b wfe_loop 228boot_entry: 229 mov w1, #0 230 str w1, [x4] 231 /* -------------------------------------------------------------------- 232 * get per cpuup boot addr 233 * -------------------------------------------------------------------- 234 */ 235 adr x5, cpuson_entry_point 236 ldr x2, [x5, x0, lsl #3] 237 238 br x2 239endfunc platform_cpu_warmboot 240 241 /* -------------------------------------------------------------------- 242 * Per-CPU Secure entry point - resume or power up 243 * -------------------------------------------------------------------- 244 */ 245 .section tzfw_coherent_mem, "a" 246 .align 3 247cpuson_entry_point: 248 .rept PLATFORM_CORE_COUNT 249 .quad 0 250 .endr 251cpuson_flags: 252 .rept PLATFORM_CORE_COUNT 253 .word 0 254 .endr 255