1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cortex_a53.h> 11#include <cortex_a72.h> 12#include <plat_private.h> 13#include <platform_def.h> 14#include <plat_pmu_macros.S> 15 16 .globl cpuson_entry_point 17 .globl cpuson_flags 18 .globl platform_cpu_warmboot 19 .globl plat_secondary_cold_boot_setup 20 .globl plat_report_exception 21 .globl platform_is_primary_cpu 22 .globl plat_crash_console_init 23 .globl plat_crash_console_putc 24 .globl plat_my_core_pos 25 .globl plat_reset_handler 26 .globl plat_panic_handler 27 28 /* 29 * void plat_reset_handler(void); 30 * 31 * Determine the SOC type and call the appropriate reset 32 * handler. 33 * 34 */ 35func plat_reset_handler 36 mrs x0, midr_el1 37 ubfx x0, x0, MIDR_PN_SHIFT, #12 38 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 39 b.eq handler_a72 40 b handler_end 41handler_a72: 42 /* 43 * This handler does the following: 44 * Set the L2 Data RAM latency for Cortex-A72. 45 * Set the L2 Tag RAM latency to for Cortex-A72. 46 */ 47 mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 48 (0x1 << 5)) 49 msr CORTEX_A72_L2CTLR_EL1, x0 50 isb 51handler_end: 52 ret 53endfunc plat_reset_handler 54 55func plat_my_core_pos 56 mrs x0, mpidr_el1 57 and x1, x0, #MPIDR_CPU_MASK 58 and x0, x0, #MPIDR_CLUSTER_MASK 59 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 60 ret 61endfunc plat_my_core_pos 62 63 /* -------------------------------------------------------------------- 64 * void plat_secondary_cold_boot_setup (void); 65 * 66 * This function performs any platform specific actions 67 * needed for a secondary cpu after a cold reset e.g 68 * mark the cpu's presence, mechanism to place it in a 69 * holding pen etc. 70 * -------------------------------------------------------------------- 71 */ 72func plat_secondary_cold_boot_setup 73 /* rk3368 does not do cold boot for secondary CPU */ 74cb_panic: 75 b cb_panic 76endfunc plat_secondary_cold_boot_setup 77 78func platform_is_primary_cpu 79 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 80 cmp x0, #PLAT_RK_PRIMARY_CPU 81 cset x0, eq 82 ret 83endfunc platform_is_primary_cpu 84 85 /* -------------------------------------------------------------------- 86 * int plat_crash_console_init(void) 87 * Function to initialize the crash console 88 * without a C Runtime to print crash report. 89 * Clobber list : x0, x1, x2 90 * -------------------------------------------------------------------- 91 */ 92func plat_crash_console_init 93 mov_imm x0, PLAT_RK_UART_BASE 94 mov_imm x1, PLAT_RK_UART_CLOCK 95 mov_imm x2, PLAT_RK_UART_BAUDRATE 96 b console_core_init 97endfunc plat_crash_console_init 98 99 /* -------------------------------------------------------------------- 100 * int plat_crash_console_putc(void) 101 * Function to print a character on the crash 102 * console without a C Runtime. 103 * Clobber list : x1, x2 104 * -------------------------------------------------------------------- 105 */ 106func plat_crash_console_putc 107 mov_imm x1, PLAT_RK_UART_BASE 108 b console_core_putc 109endfunc plat_crash_console_putc 110 111 /* -------------------------------------------------------------------- 112 * void plat_panic_handler(void) 113 * Call system reset function on panic. Set up an emergency stack so we 114 * can run C functions (it only needs to last for a few calls until we 115 * reboot anyway). 116 * -------------------------------------------------------------------- 117 */ 118func plat_panic_handler 119 msr spsel, #0 120 bl plat_set_my_stack 121 b rockchip_soc_soft_reset 122endfunc plat_panic_handler 123 124 /* -------------------------------------------------------------------- 125 * void platform_cpu_warmboot (void); 126 * cpus online or resume enterpoint 127 * -------------------------------------------------------------------- 128 */ 129func platform_cpu_warmboot _align=16 130 mrs x0, MPIDR_EL1 131 and x19, x0, #MPIDR_CPU_MASK 132 and x20, x0, #MPIDR_CLUSTER_MASK 133 mov x0, x20 134 func_rockchip_clst_warmboot 135 /* -------------------------------------------------------------------- 136 * big cluster id is 1 137 * big cores id is from 0-3, little cores id 4-7 138 * -------------------------------------------------------------------- 139 */ 140 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 141 /* -------------------------------------------------------------------- 142 * get per cpuup flag 143 * -------------------------------------------------------------------- 144 */ 145 adr x4, cpuson_flags 146 add x4, x4, x21, lsl #2 147 ldr w1, [x4] 148 /* -------------------------------------------------------------------- 149 * check cpuon reason 150 * -------------------------------------------------------------------- 151 */ 152 cmp w1, PMU_CPU_AUTO_PWRDN 153 b.eq boot_entry 154 cmp w1, PMU_CPU_HOTPLUG 155 b.eq boot_entry 156 /* -------------------------------------------------------------------- 157 * If the boot core cpuson_flags or cpuson_entry_point is not 158 * expection. force the core into wfe. 159 * -------------------------------------------------------------------- 160 */ 161wfe_loop: 162 wfe 163 b wfe_loop 164boot_entry: 165 str wzr, [x4] 166 /* -------------------------------------------------------------------- 167 * get per cpuup boot addr 168 * -------------------------------------------------------------------- 169 */ 170 adr x5, cpuson_entry_point 171 ldr x2, [x5, x21, lsl #3] 172 br x2 173endfunc platform_cpu_warmboot 174 175 /* -------------------------------------------------------------------- 176 * Per-CPU Secure entry point - resume or power up 177 * -------------------------------------------------------------------- 178 */ 179 .section tzfw_coherent_mem, "a" 180 .align 3 181cpuson_entry_point: 182 .rept PLATFORM_CORE_COUNT 183 .quad 0 184 .endr 185cpuson_flags: 186 .rept PLATFORM_CORE_COUNT 187 .word 0 188 .endr 189rockchip_clst_warmboot_data 190