1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cortex_a53.h> 11#include <cortex_a72.h> 12#include <plat_private.h> 13#include <platform_def.h> 14#include <plat_pmu_macros.S> 15 16 .globl cpuson_entry_point 17 .globl cpuson_flags 18 .globl platform_cpu_warmboot 19 .globl plat_secondary_cold_boot_setup 20 .globl plat_report_exception 21 .globl plat_is_my_cpu_primary 22 .globl plat_my_core_pos 23 .globl plat_reset_handler 24 .globl plat_panic_handler 25 26 /* 27 * void plat_reset_handler(void); 28 * 29 * Determine the SOC type and call the appropriate reset 30 * handler. 31 * 32 */ 33func plat_reset_handler 34 mrs x0, midr_el1 35 ubfx x0, x0, MIDR_PN_SHIFT, #12 36 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 37 b.eq handler_a72 38 b handler_end 39handler_a72: 40 /* 41 * This handler does the following: 42 * Set the L2 Data RAM latency for Cortex-A72. 43 * Set the L2 Tag RAM latency to for Cortex-A72. 44 */ 45 mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 46 (0x1 << 5)) 47 msr CORTEX_A72_L2CTLR_EL1, x0 48 isb 49handler_end: 50 ret 51endfunc plat_reset_handler 52 53func plat_my_core_pos 54 mrs x0, mpidr_el1 55 and x1, x0, #MPIDR_CPU_MASK 56 and x0, x0, #MPIDR_CLUSTER_MASK 57 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 58 ret 59endfunc plat_my_core_pos 60 61 /* -------------------------------------------------------------------- 62 * void plat_secondary_cold_boot_setup (void); 63 * 64 * This function performs any platform specific actions 65 * needed for a secondary cpu after a cold reset e.g 66 * mark the cpu's presence, mechanism to place it in a 67 * holding pen etc. 68 * -------------------------------------------------------------------- 69 */ 70func plat_secondary_cold_boot_setup 71 /* rk3368 does not do cold boot for secondary CPU */ 72cb_panic: 73 b cb_panic 74endfunc plat_secondary_cold_boot_setup 75 76func plat_is_my_cpu_primary 77 mrs x0, mpidr_el1 78 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 79 cmp x0, #PLAT_RK_PRIMARY_CPU 80 cset x0, eq 81 ret 82endfunc plat_is_my_cpu_primary 83 84 /* -------------------------------------------------------------------- 85 * void plat_panic_handler(void) 86 * Call system reset function on panic. Set up an emergency stack so we 87 * can run C functions (it only needs to last for a few calls until we 88 * reboot anyway). 89 * -------------------------------------------------------------------- 90 */ 91func plat_panic_handler 92 msr spsel, #0 93 bl plat_set_my_stack 94 b rockchip_soc_soft_reset 95endfunc plat_panic_handler 96 97 /* -------------------------------------------------------------------- 98 * void platform_cpu_warmboot (void); 99 * cpus online or resume enterpoint 100 * -------------------------------------------------------------------- 101 */ 102func platform_cpu_warmboot _align=16 103 mrs x0, MPIDR_EL1 104 and x19, x0, #MPIDR_CPU_MASK 105 and x20, x0, #MPIDR_CLUSTER_MASK 106 mov x0, x20 107 func_rockchip_clst_warmboot 108 /* -------------------------------------------------------------------- 109 * big cluster id is 1 110 * big cores id is from 0-3, little cores id 4-7 111 * -------------------------------------------------------------------- 112 */ 113 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 114 /* -------------------------------------------------------------------- 115 * get per cpuup flag 116 * -------------------------------------------------------------------- 117 */ 118 adr x4, cpuson_flags 119 add x4, x4, x21, lsl #2 120 ldr w1, [x4] 121 /* -------------------------------------------------------------------- 122 * check cpuon reason 123 * -------------------------------------------------------------------- 124 */ 125 cmp w1, PMU_CPU_AUTO_PWRDN 126 b.eq boot_entry 127 cmp w1, PMU_CPU_HOTPLUG 128 b.eq boot_entry 129 /* -------------------------------------------------------------------- 130 * If the boot core cpuson_flags or cpuson_entry_point is not 131 * expection. force the core into wfe. 132 * -------------------------------------------------------------------- 133 */ 134wfe_loop: 135 wfe 136 b wfe_loop 137boot_entry: 138 str wzr, [x4] 139 /* -------------------------------------------------------------------- 140 * get per cpuup boot addr 141 * -------------------------------------------------------------------- 142 */ 143 adr x5, cpuson_entry_point 144 ldr x2, [x5, x21, lsl #3] 145 br x2 146endfunc platform_cpu_warmboot 147 148 /* -------------------------------------------------------------------- 149 * Per-CPU Secure entry point - resume or power up 150 * -------------------------------------------------------------------- 151 */ 152 .section tzfw_coherent_mem, "a" 153 .align 3 154cpuson_entry_point: 155 .rept PLATFORM_CORE_COUNT 156 .quad 0 157 .endr 158cpuson_flags: 159 .rept PLATFORM_CORE_COUNT 160 .word 0 161 .endr 162rockchip_clst_warmboot_data 163