1/* 2 * Copyright (c) 2013-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <common/bl_common.h> 12#include <cortex_a53.h> 13#include <cortex_a72.h> 14#include <plat_private.h> 15#include <plat_pmu_macros.S> 16 17 .globl cpuson_entry_point 18 .globl cpuson_flags 19 .globl platform_cpu_warmboot 20 .globl plat_secondary_cold_boot_setup 21 .globl plat_report_exception 22 .globl plat_is_my_cpu_primary 23 .globl plat_my_core_pos 24 .globl plat_reset_handler 25 .globl plat_panic_handler 26 27 /* 28 * void plat_reset_handler(void); 29 * 30 * Determine the SOC type and call the appropriate reset 31 * handler. 32 * 33 */ 34func plat_reset_handler 35#ifdef PLAT_RK_CPU_RESET_EARLY 36 mov x18, x30 37 msr spsel, #0 38 bl plat_set_my_stack 39 mov x0, x20 40 mov x1, x21 41 mov x2, x22 42 mov x3, x23 43 bl rockchip_cpu_reset_early 44 mov x30, x18 45#endif 46 mrs x0, midr_el1 47 ubfx x0, x0, MIDR_PN_SHIFT, #12 48 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 49 b.eq handler_a72 50 b handler_end 51handler_a72: 52 /* 53 * This handler does the following: 54 * Set the L2 Data RAM latency for Cortex-A72. 55 * Set the L2 Tag RAM latency to for Cortex-A72. 56 */ 57 mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 58 (0x1 << 5)) 59 msr CORTEX_A72_L2CTLR_EL1, x0 60 isb 61handler_end: 62 ret 63endfunc plat_reset_handler 64 65func plat_my_core_pos 66 mrs x0, mpidr_el1 67 and x1, x0, #MPIDR_CPU_MASK 68 and x0, x0, #MPIDR_CLUSTER_MASK 69 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 70 ret 71endfunc plat_my_core_pos 72 73 /* -------------------------------------------------------------------- 74 * void plat_secondary_cold_boot_setup (void); 75 * 76 * This function performs any platform specific actions 77 * needed for a secondary cpu after a cold reset e.g 78 * mark the cpu's presence, mechanism to place it in a 79 * holding pen etc. 80 * -------------------------------------------------------------------- 81 */ 82func plat_secondary_cold_boot_setup 83 /* rk3368 does not do cold boot for secondary CPU */ 84cb_panic: 85 b cb_panic 86endfunc plat_secondary_cold_boot_setup 87 88func plat_is_my_cpu_primary 89 mrs x0, mpidr_el1 90 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 91 cmp x0, #PLAT_RK_PRIMARY_CPU 92 cset x0, eq 93 ret 94endfunc plat_is_my_cpu_primary 95 96 /* -------------------------------------------------------------------- 97 * void plat_panic_handler(void) 98 * Call system reset function on panic. Set up an emergency stack so we 99 * can run C functions (it only needs to last for a few calls until we 100 * reboot anyway). 101 * -------------------------------------------------------------------- 102 */ 103func plat_panic_handler 104 msr spsel, #0 105 bl plat_set_my_stack 106 b rockchip_soc_soft_reset 107endfunc plat_panic_handler 108 109 /* -------------------------------------------------------------------- 110 * void platform_cpu_warmboot (void); 111 * cpus online or resume enterpoint 112 * -------------------------------------------------------------------- 113 */ 114func platform_cpu_warmboot _align=16 115 mrs x0, MPIDR_EL1 116 and x19, x0, #MPIDR_CPU_MASK 117 and x20, x0, #MPIDR_CLUSTER_MASK 118 mov x0, x20 119 func_rockchip_clst_warmboot 120 /* -------------------------------------------------------------------- 121 * big cluster id is 1 122 * big cores id is from 0-3, little cores id 4-7 123 * -------------------------------------------------------------------- 124 */ 125 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 126 /* -------------------------------------------------------------------- 127 * get per cpuup flag 128 * -------------------------------------------------------------------- 129 */ 130 adr x4, cpuson_flags 131 add x4, x4, x21, lsl #2 132 ldr w1, [x4] 133 /* -------------------------------------------------------------------- 134 * check cpuon reason 135 * -------------------------------------------------------------------- 136 */ 137 cmp w1, PMU_CPU_AUTO_PWRDN 138 b.eq boot_entry 139 cmp w1, PMU_CPU_HOTPLUG 140 b.eq boot_entry 141 /* -------------------------------------------------------------------- 142 * If the boot core cpuson_flags or cpuson_entry_point is not 143 * expection. force the core into wfe. 144 * -------------------------------------------------------------------- 145 */ 146wfe_loop: 147 wfe 148 b wfe_loop 149boot_entry: 150 str wzr, [x4] 151 /* -------------------------------------------------------------------- 152 * get per cpuup boot addr 153 * -------------------------------------------------------------------- 154 */ 155 adr x5, cpuson_entry_point 156 ldr x2, [x5, x21, lsl #3] 157 br x2 158endfunc platform_cpu_warmboot 159 160 /* -------------------------------------------------------------------- 161 * Per-CPU Secure entry point - resume or power up 162 * -------------------------------------------------------------------- 163 */ 164 165#if USE_COHERENT_MEM 166 .section .tzfw_coherent_mem, "a" 167#else 168 .data 169#endif 170 .align 3 171cpuson_entry_point: 172 .rept PLATFORM_CORE_COUNT 173 .quad 0 174 .endr 175cpuson_flags: 176 .rept PLATFORM_CORE_COUNT 177 .word 0 178 .endr 179rockchip_clst_warmboot_data 180