16fba6e04STony Xie/* 26fba6e04STony Xie * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 76fba6e04STony Xie#include <arch.h> 86fba6e04STony Xie#include <asm_macros.S> 96fba6e04STony Xie#include <bl_common.h> 106fba6e04STony Xie#include <cortex_a53.h> 116fba6e04STony Xie#include <cortex_a72.h> 126fba6e04STony Xie#include <plat_private.h> 136fba6e04STony Xie#include <platform_def.h> 149ec78bdfSTony Xie#include <plat_pmu_macros.S> 156fba6e04STony Xie 166fba6e04STony Xie .globl cpuson_entry_point 176fba6e04STony Xie .globl cpuson_flags 186fba6e04STony Xie .globl platform_cpu_warmboot 196fba6e04STony Xie .globl plat_secondary_cold_boot_setup 206fba6e04STony Xie .globl plat_report_exception 216fba6e04STony Xie .globl platform_is_primary_cpu 226fba6e04STony Xie .globl plat_crash_console_init 236fba6e04STony Xie .globl plat_crash_console_putc 246fba6e04STony Xie .globl plat_my_core_pos 256fba6e04STony Xie .globl plat_reset_handler 266fba6e04STony Xie 276fba6e04STony Xie /* 286fba6e04STony Xie * void plat_reset_handler(void); 296fba6e04STony Xie * 306fba6e04STony Xie * Determine the SOC type and call the appropriate reset 316fba6e04STony Xie * handler. 326fba6e04STony Xie * 336fba6e04STony Xie */ 346fba6e04STony Xiefunc plat_reset_handler 359ec78bdfSTony Xie mrs x0, midr_el1 369ec78bdfSTony Xie ubfx x0, x0, MIDR_PN_SHIFT, #12 379ec78bdfSTony Xie cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 389ec78bdfSTony Xie b.eq handler_a72 399ec78bdfSTony Xie b handler_end 409ec78bdfSTony Xiehandler_a72: 419ec78bdfSTony Xie /* 429ec78bdfSTony Xie * This handler does the following: 439ec78bdfSTony Xie * Set the L2 Data RAM latency for Cortex-A72. 449ec78bdfSTony Xie * Set the L2 Tag RAM latency to for Cortex-A72. 459ec78bdfSTony Xie */ 46*fb7d32e5SVarun Wadekar mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 479ec78bdfSTony Xie (0x1 << 5)) 48*fb7d32e5SVarun Wadekar msr CORTEX_A72_L2CTLR_EL1, x0 499ec78bdfSTony Xie isb 509ec78bdfSTony Xiehandler_end: 519ec78bdfSTony Xie ret 526fba6e04STony Xieendfunc plat_reset_handler 536fba6e04STony Xie 546fba6e04STony Xiefunc plat_my_core_pos 556fba6e04STony Xie mrs x0, mpidr_el1 566fba6e04STony Xie and x1, x0, #MPIDR_CPU_MASK 576fba6e04STony Xie and x0, x0, #MPIDR_CLUSTER_MASK 589ec78bdfSTony Xie add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 596fba6e04STony Xie ret 606fba6e04STony Xieendfunc plat_my_core_pos 616fba6e04STony Xie 626fba6e04STony Xie /* -------------------------------------------------------------------- 636fba6e04STony Xie * void plat_secondary_cold_boot_setup (void); 646fba6e04STony Xie * 656fba6e04STony Xie * This function performs any platform specific actions 666fba6e04STony Xie * needed for a secondary cpu after a cold reset e.g 676fba6e04STony Xie * mark the cpu's presence, mechanism to place it in a 686fba6e04STony Xie * holding pen etc. 696fba6e04STony Xie * -------------------------------------------------------------------- 706fba6e04STony Xie */ 716fba6e04STony Xiefunc plat_secondary_cold_boot_setup 726fba6e04STony Xie /* rk3368 does not do cold boot for secondary CPU */ 736fba6e04STony Xiecb_panic: 746fba6e04STony Xie b cb_panic 756fba6e04STony Xieendfunc plat_secondary_cold_boot_setup 766fba6e04STony Xie 776fba6e04STony Xiefunc platform_is_primary_cpu 786fba6e04STony Xie and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 796fba6e04STony Xie cmp x0, #PLAT_RK_PRIMARY_CPU 806fba6e04STony Xie cset x0, eq 816fba6e04STony Xie ret 826fba6e04STony Xieendfunc platform_is_primary_cpu 836fba6e04STony Xie 846fba6e04STony Xie /* -------------------------------------------------------------------- 856fba6e04STony Xie * int plat_crash_console_init(void) 866fba6e04STony Xie * Function to initialize the crash console 876fba6e04STony Xie * without a C Runtime to print crash report. 886fba6e04STony Xie * Clobber list : x0, x1, x2 896fba6e04STony Xie * -------------------------------------------------------------------- 906fba6e04STony Xie */ 916fba6e04STony Xiefunc plat_crash_console_init 926fba6e04STony Xie mov_imm x0, PLAT_RK_UART_BASE 936fba6e04STony Xie mov_imm x1, PLAT_RK_UART_CLOCK 946fba6e04STony Xie mov_imm x2, PLAT_RK_UART_BAUDRATE 956fba6e04STony Xie b console_core_init 966fba6e04STony Xieendfunc plat_crash_console_init 976fba6e04STony Xie 986fba6e04STony Xie /* -------------------------------------------------------------------- 996fba6e04STony Xie * int plat_crash_console_putc(void) 1006fba6e04STony Xie * Function to print a character on the crash 1016fba6e04STony Xie * console without a C Runtime. 1026fba6e04STony Xie * Clobber list : x1, x2 1036fba6e04STony Xie * -------------------------------------------------------------------- 1046fba6e04STony Xie */ 1056fba6e04STony Xiefunc plat_crash_console_putc 1066fba6e04STony Xie mov_imm x1, PLAT_RK_UART_BASE 1076fba6e04STony Xie b console_core_putc 1086fba6e04STony Xieendfunc plat_crash_console_putc 1096fba6e04STony Xie 1106fba6e04STony Xie /* -------------------------------------------------------------------- 1116fba6e04STony Xie * void platform_cpu_warmboot (void); 1126fba6e04STony Xie * cpus online or resume enterpoint 1136fba6e04STony Xie * -------------------------------------------------------------------- 1146fba6e04STony Xie */ 115f47a25ddSCaesar Wang .align 16 1166fba6e04STony Xiefunc platform_cpu_warmboot 1176fba6e04STony Xie mrs x0, MPIDR_EL1 1189ec78bdfSTony Xie and x19, x0, #MPIDR_CPU_MASK 1199ec78bdfSTony Xie and x20, x0, #MPIDR_CLUSTER_MASK 1209ec78bdfSTony Xie mov x0, x20 1219ec78bdfSTony Xie func_rockchip_clst_warmboot 1226fba6e04STony Xie /* -------------------------------------------------------------------- 1236fba6e04STony Xie * big cluster id is 1 1246fba6e04STony Xie * big cores id is from 0-3, little cores id 4-7 1256fba6e04STony Xie * -------------------------------------------------------------------- 1266fba6e04STony Xie */ 1279ec78bdfSTony Xie add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 1286fba6e04STony Xie /* -------------------------------------------------------------------- 1296fba6e04STony Xie * get per cpuup flag 1306fba6e04STony Xie * -------------------------------------------------------------------- 1316fba6e04STony Xie */ 1326fba6e04STony Xie adr x4, cpuson_flags 1339ec78bdfSTony Xie add x4, x4, x21, lsl #2 1346fba6e04STony Xie ldr w1, [x4] 1356fba6e04STony Xie /* -------------------------------------------------------------------- 1366fba6e04STony Xie * check cpuon reason 1376fba6e04STony Xie * -------------------------------------------------------------------- 1386fba6e04STony Xie */ 1399ec78bdfSTony Xie cmp w1, PMU_CPU_AUTO_PWRDN 1406fba6e04STony Xie b.eq boot_entry 1419ec78bdfSTony Xie cmp w1, PMU_CPU_HOTPLUG 1426fba6e04STony Xie b.eq boot_entry 1436fba6e04STony Xie /* -------------------------------------------------------------------- 1446fba6e04STony Xie * If the boot core cpuson_flags or cpuson_entry_point is not 1456fba6e04STony Xie * expection. force the core into wfe. 1466fba6e04STony Xie * -------------------------------------------------------------------- 1476fba6e04STony Xie */ 1486fba6e04STony Xiewfe_loop: 1496fba6e04STony Xie wfe 1506fba6e04STony Xie b wfe_loop 1516fba6e04STony Xieboot_entry: 1529ec78bdfSTony Xie str wzr, [x4] 153f47a25ddSCaesar Wang /* -------------------------------------------------------------------- 154f47a25ddSCaesar Wang * get per cpuup boot addr 155f47a25ddSCaesar Wang * -------------------------------------------------------------------- 156f47a25ddSCaesar Wang */ 157f47a25ddSCaesar Wang adr x5, cpuson_entry_point 1589ec78bdfSTony Xie ldr x2, [x5, x21, lsl #3] 1596fba6e04STony Xie br x2 1606fba6e04STony Xieendfunc platform_cpu_warmboot 1616fba6e04STony Xie 1626fba6e04STony Xie /* -------------------------------------------------------------------- 1636fba6e04STony Xie * Per-CPU Secure entry point - resume or power up 1646fba6e04STony Xie * -------------------------------------------------------------------- 1656fba6e04STony Xie */ 1666fba6e04STony Xie .section tzfw_coherent_mem, "a" 1676fba6e04STony Xie .align 3 1686fba6e04STony Xiecpuson_entry_point: 1696fba6e04STony Xie .rept PLATFORM_CORE_COUNT 1706fba6e04STony Xie .quad 0 1716fba6e04STony Xie .endr 1726fba6e04STony Xiecpuson_flags: 1736fba6e04STony Xie .rept PLATFORM_CORE_COUNT 174f47a25ddSCaesar Wang .word 0 1756fba6e04STony Xie .endr 1769ec78bdfSTony Xierockchip_clst_warmboot_data 177