16fba6e04STony Xie/* 26fba6e04STony Xie * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 709d40e0eSAntonio Nino Diaz#include <platform_def.h> 809d40e0eSAntonio Nino Diaz 96fba6e04STony Xie#include <arch.h> 106fba6e04STony Xie#include <asm_macros.S> 1109d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 126fba6e04STony Xie#include <cortex_a53.h> 136fba6e04STony Xie#include <cortex_a72.h> 146fba6e04STony Xie#include <plat_private.h> 159ec78bdfSTony Xie#include <plat_pmu_macros.S> 166fba6e04STony Xie 176fba6e04STony Xie .globl cpuson_entry_point 186fba6e04STony Xie .globl cpuson_flags 196fba6e04STony Xie .globl platform_cpu_warmboot 206fba6e04STony Xie .globl plat_secondary_cold_boot_setup 216fba6e04STony Xie .globl plat_report_exception 225eddd22eSDaniel Boulby .globl plat_is_my_cpu_primary 236fba6e04STony Xie .globl plat_my_core_pos 246fba6e04STony Xie .globl plat_reset_handler 25a33e763cSJulius Werner .globl plat_panic_handler 266fba6e04STony Xie 276fba6e04STony Xie /* 286fba6e04STony Xie * void plat_reset_handler(void); 296fba6e04STony Xie * 306fba6e04STony Xie * Determine the SOC type and call the appropriate reset 316fba6e04STony Xie * handler. 326fba6e04STony Xie * 336fba6e04STony Xie */ 346fba6e04STony Xiefunc plat_reset_handler 359ec78bdfSTony Xie mrs x0, midr_el1 369ec78bdfSTony Xie ubfx x0, x0, MIDR_PN_SHIFT, #12 379ec78bdfSTony Xie cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 389ec78bdfSTony Xie b.eq handler_a72 399ec78bdfSTony Xie b handler_end 409ec78bdfSTony Xiehandler_a72: 419ec78bdfSTony Xie /* 429ec78bdfSTony Xie * This handler does the following: 439ec78bdfSTony Xie * Set the L2 Data RAM latency for Cortex-A72. 449ec78bdfSTony Xie * Set the L2 Tag RAM latency to for Cortex-A72. 459ec78bdfSTony Xie */ 46fb7d32e5SVarun Wadekar mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 479ec78bdfSTony Xie (0x1 << 5)) 48fb7d32e5SVarun Wadekar msr CORTEX_A72_L2CTLR_EL1, x0 499ec78bdfSTony Xie isb 509ec78bdfSTony Xiehandler_end: 519ec78bdfSTony Xie ret 526fba6e04STony Xieendfunc plat_reset_handler 536fba6e04STony Xie 546fba6e04STony Xiefunc plat_my_core_pos 556fba6e04STony Xie mrs x0, mpidr_el1 566fba6e04STony Xie and x1, x0, #MPIDR_CPU_MASK 576fba6e04STony Xie and x0, x0, #MPIDR_CLUSTER_MASK 589ec78bdfSTony Xie add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 596fba6e04STony Xie ret 606fba6e04STony Xieendfunc plat_my_core_pos 616fba6e04STony Xie 626fba6e04STony Xie /* -------------------------------------------------------------------- 636fba6e04STony Xie * void plat_secondary_cold_boot_setup (void); 646fba6e04STony Xie * 656fba6e04STony Xie * This function performs any platform specific actions 666fba6e04STony Xie * needed for a secondary cpu after a cold reset e.g 676fba6e04STony Xie * mark the cpu's presence, mechanism to place it in a 686fba6e04STony Xie * holding pen etc. 696fba6e04STony Xie * -------------------------------------------------------------------- 706fba6e04STony Xie */ 716fba6e04STony Xiefunc plat_secondary_cold_boot_setup 726fba6e04STony Xie /* rk3368 does not do cold boot for secondary CPU */ 736fba6e04STony Xiecb_panic: 746fba6e04STony Xie b cb_panic 756fba6e04STony Xieendfunc plat_secondary_cold_boot_setup 766fba6e04STony Xie 775eddd22eSDaniel Boulbyfunc plat_is_my_cpu_primary 785eddd22eSDaniel Boulby mrs x0, mpidr_el1 796fba6e04STony Xie and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 806fba6e04STony Xie cmp x0, #PLAT_RK_PRIMARY_CPU 816fba6e04STony Xie cset x0, eq 826fba6e04STony Xie ret 835eddd22eSDaniel Boulbyendfunc plat_is_my_cpu_primary 846fba6e04STony Xie 856fba6e04STony Xie /* -------------------------------------------------------------------- 86a33e763cSJulius Werner * void plat_panic_handler(void) 87a33e763cSJulius Werner * Call system reset function on panic. Set up an emergency stack so we 88a33e763cSJulius Werner * can run C functions (it only needs to last for a few calls until we 89a33e763cSJulius Werner * reboot anyway). 90a33e763cSJulius Werner * -------------------------------------------------------------------- 91a33e763cSJulius Werner */ 92a33e763cSJulius Wernerfunc plat_panic_handler 93a33e763cSJulius Werner msr spsel, #0 94a33e763cSJulius Werner bl plat_set_my_stack 95a33e763cSJulius Werner b rockchip_soc_soft_reset 96a33e763cSJulius Wernerendfunc plat_panic_handler 97a33e763cSJulius Werner 98a33e763cSJulius Werner /* -------------------------------------------------------------------- 996fba6e04STony Xie * void platform_cpu_warmboot (void); 1006fba6e04STony Xie * cpus online or resume enterpoint 1016fba6e04STony Xie * -------------------------------------------------------------------- 1026fba6e04STony Xie */ 10364726e6dSJulius Wernerfunc platform_cpu_warmboot _align=16 1046fba6e04STony Xie mrs x0, MPIDR_EL1 1059ec78bdfSTony Xie and x19, x0, #MPIDR_CPU_MASK 1069ec78bdfSTony Xie and x20, x0, #MPIDR_CLUSTER_MASK 1079ec78bdfSTony Xie mov x0, x20 1089ec78bdfSTony Xie func_rockchip_clst_warmboot 1096fba6e04STony Xie /* -------------------------------------------------------------------- 1106fba6e04STony Xie * big cluster id is 1 1116fba6e04STony Xie * big cores id is from 0-3, little cores id 4-7 1126fba6e04STony Xie * -------------------------------------------------------------------- 1136fba6e04STony Xie */ 1149ec78bdfSTony Xie add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 1156fba6e04STony Xie /* -------------------------------------------------------------------- 1166fba6e04STony Xie * get per cpuup flag 1176fba6e04STony Xie * -------------------------------------------------------------------- 1186fba6e04STony Xie */ 1196fba6e04STony Xie adr x4, cpuson_flags 1209ec78bdfSTony Xie add x4, x4, x21, lsl #2 1216fba6e04STony Xie ldr w1, [x4] 1226fba6e04STony Xie /* -------------------------------------------------------------------- 1236fba6e04STony Xie * check cpuon reason 1246fba6e04STony Xie * -------------------------------------------------------------------- 1256fba6e04STony Xie */ 1269ec78bdfSTony Xie cmp w1, PMU_CPU_AUTO_PWRDN 1276fba6e04STony Xie b.eq boot_entry 1289ec78bdfSTony Xie cmp w1, PMU_CPU_HOTPLUG 1296fba6e04STony Xie b.eq boot_entry 1306fba6e04STony Xie /* -------------------------------------------------------------------- 1316fba6e04STony Xie * If the boot core cpuson_flags or cpuson_entry_point is not 1326fba6e04STony Xie * expection. force the core into wfe. 1336fba6e04STony Xie * -------------------------------------------------------------------- 1346fba6e04STony Xie */ 1356fba6e04STony Xiewfe_loop: 1366fba6e04STony Xie wfe 1376fba6e04STony Xie b wfe_loop 1386fba6e04STony Xieboot_entry: 1399ec78bdfSTony Xie str wzr, [x4] 140f47a25ddSCaesar Wang /* -------------------------------------------------------------------- 141f47a25ddSCaesar Wang * get per cpuup boot addr 142f47a25ddSCaesar Wang * -------------------------------------------------------------------- 143f47a25ddSCaesar Wang */ 144f47a25ddSCaesar Wang adr x5, cpuson_entry_point 1459ec78bdfSTony Xie ldr x2, [x5, x21, lsl #3] 1466fba6e04STony Xie br x2 1476fba6e04STony Xieendfunc platform_cpu_warmboot 1486fba6e04STony Xie 1496fba6e04STony Xie /* -------------------------------------------------------------------- 1506fba6e04STony Xie * Per-CPU Secure entry point - resume or power up 1516fba6e04STony Xie * -------------------------------------------------------------------- 1526fba6e04STony Xie */ 153*da04341eSChris Kay .section .tzfw_coherent_mem, "a" 1546fba6e04STony Xie .align 3 1556fba6e04STony Xiecpuson_entry_point: 1566fba6e04STony Xie .rept PLATFORM_CORE_COUNT 1576fba6e04STony Xie .quad 0 1586fba6e04STony Xie .endr 1596fba6e04STony Xiecpuson_flags: 1606fba6e04STony Xie .rept PLATFORM_CORE_COUNT 161f47a25ddSCaesar Wang .word 0 1626fba6e04STony Xie .endr 1639ec78bdfSTony Xierockchip_clst_warmboot_data 164