16fba6e04STony Xie/* 2*b833bbe6SXiaoDong Huang * Copyright (c) 2013-2024, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 709d40e0eSAntonio Nino Diaz#include <platform_def.h> 809d40e0eSAntonio Nino Diaz 96fba6e04STony Xie#include <arch.h> 106fba6e04STony Xie#include <asm_macros.S> 1109d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 126fba6e04STony Xie#include <cortex_a53.h> 136fba6e04STony Xie#include <cortex_a72.h> 146fba6e04STony Xie#include <plat_private.h> 159ec78bdfSTony Xie#include <plat_pmu_macros.S> 166fba6e04STony Xie 176fba6e04STony Xie .globl cpuson_entry_point 186fba6e04STony Xie .globl cpuson_flags 196fba6e04STony Xie .globl platform_cpu_warmboot 206fba6e04STony Xie .globl plat_secondary_cold_boot_setup 216fba6e04STony Xie .globl plat_report_exception 225eddd22eSDaniel Boulby .globl plat_is_my_cpu_primary 236fba6e04STony Xie .globl plat_my_core_pos 246fba6e04STony Xie .globl plat_reset_handler 25a33e763cSJulius Werner .globl plat_panic_handler 266fba6e04STony Xie 276fba6e04STony Xie /* 286fba6e04STony Xie * void plat_reset_handler(void); 296fba6e04STony Xie * 306fba6e04STony Xie * Determine the SOC type and call the appropriate reset 316fba6e04STony Xie * handler. 326fba6e04STony Xie * 336fba6e04STony Xie */ 346fba6e04STony Xiefunc plat_reset_handler 35*b833bbe6SXiaoDong Huang#ifdef PLAT_RK_CPU_RESET_EARLY 36*b833bbe6SXiaoDong Huang mov x18, x30 37*b833bbe6SXiaoDong Huang msr spsel, #0 38*b833bbe6SXiaoDong Huang bl plat_set_my_stack 39*b833bbe6SXiaoDong Huang mov x0, x20 40*b833bbe6SXiaoDong Huang mov x1, x21 41*b833bbe6SXiaoDong Huang mov x2, x22 42*b833bbe6SXiaoDong Huang mov x3, x23 43*b833bbe6SXiaoDong Huang bl rockchip_cpu_reset_early 44*b833bbe6SXiaoDong Huang mov x30, x18 45*b833bbe6SXiaoDong Huang#endif 469ec78bdfSTony Xie mrs x0, midr_el1 479ec78bdfSTony Xie ubfx x0, x0, MIDR_PN_SHIFT, #12 489ec78bdfSTony Xie cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 499ec78bdfSTony Xie b.eq handler_a72 509ec78bdfSTony Xie b handler_end 519ec78bdfSTony Xiehandler_a72: 529ec78bdfSTony Xie /* 539ec78bdfSTony Xie * This handler does the following: 549ec78bdfSTony Xie * Set the L2 Data RAM latency for Cortex-A72. 559ec78bdfSTony Xie * Set the L2 Tag RAM latency to for Cortex-A72. 569ec78bdfSTony Xie */ 57fb7d32e5SVarun Wadekar mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 589ec78bdfSTony Xie (0x1 << 5)) 59fb7d32e5SVarun Wadekar msr CORTEX_A72_L2CTLR_EL1, x0 609ec78bdfSTony Xie isb 619ec78bdfSTony Xiehandler_end: 629ec78bdfSTony Xie ret 636fba6e04STony Xieendfunc plat_reset_handler 646fba6e04STony Xie 656fba6e04STony Xiefunc plat_my_core_pos 666fba6e04STony Xie mrs x0, mpidr_el1 676fba6e04STony Xie and x1, x0, #MPIDR_CPU_MASK 686fba6e04STony Xie and x0, x0, #MPIDR_CLUSTER_MASK 699ec78bdfSTony Xie add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 706fba6e04STony Xie ret 716fba6e04STony Xieendfunc plat_my_core_pos 726fba6e04STony Xie 736fba6e04STony Xie /* -------------------------------------------------------------------- 746fba6e04STony Xie * void plat_secondary_cold_boot_setup (void); 756fba6e04STony Xie * 766fba6e04STony Xie * This function performs any platform specific actions 776fba6e04STony Xie * needed for a secondary cpu after a cold reset e.g 786fba6e04STony Xie * mark the cpu's presence, mechanism to place it in a 796fba6e04STony Xie * holding pen etc. 806fba6e04STony Xie * -------------------------------------------------------------------- 816fba6e04STony Xie */ 826fba6e04STony Xiefunc plat_secondary_cold_boot_setup 836fba6e04STony Xie /* rk3368 does not do cold boot for secondary CPU */ 846fba6e04STony Xiecb_panic: 856fba6e04STony Xie b cb_panic 866fba6e04STony Xieendfunc plat_secondary_cold_boot_setup 876fba6e04STony Xie 885eddd22eSDaniel Boulbyfunc plat_is_my_cpu_primary 895eddd22eSDaniel Boulby mrs x0, mpidr_el1 906fba6e04STony Xie and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 916fba6e04STony Xie cmp x0, #PLAT_RK_PRIMARY_CPU 926fba6e04STony Xie cset x0, eq 936fba6e04STony Xie ret 945eddd22eSDaniel Boulbyendfunc plat_is_my_cpu_primary 956fba6e04STony Xie 966fba6e04STony Xie /* -------------------------------------------------------------------- 97a33e763cSJulius Werner * void plat_panic_handler(void) 98a33e763cSJulius Werner * Call system reset function on panic. Set up an emergency stack so we 99a33e763cSJulius Werner * can run C functions (it only needs to last for a few calls until we 100a33e763cSJulius Werner * reboot anyway). 101a33e763cSJulius Werner * -------------------------------------------------------------------- 102a33e763cSJulius Werner */ 103a33e763cSJulius Wernerfunc plat_panic_handler 104a33e763cSJulius Werner msr spsel, #0 105a33e763cSJulius Werner bl plat_set_my_stack 106a33e763cSJulius Werner b rockchip_soc_soft_reset 107a33e763cSJulius Wernerendfunc plat_panic_handler 108a33e763cSJulius Werner 109a33e763cSJulius Werner /* -------------------------------------------------------------------- 1106fba6e04STony Xie * void platform_cpu_warmboot (void); 1116fba6e04STony Xie * cpus online or resume enterpoint 1126fba6e04STony Xie * -------------------------------------------------------------------- 1136fba6e04STony Xie */ 11464726e6dSJulius Wernerfunc platform_cpu_warmboot _align=16 1156fba6e04STony Xie mrs x0, MPIDR_EL1 1169ec78bdfSTony Xie and x19, x0, #MPIDR_CPU_MASK 1179ec78bdfSTony Xie and x20, x0, #MPIDR_CLUSTER_MASK 1189ec78bdfSTony Xie mov x0, x20 1199ec78bdfSTony Xie func_rockchip_clst_warmboot 1206fba6e04STony Xie /* -------------------------------------------------------------------- 1216fba6e04STony Xie * big cluster id is 1 1226fba6e04STony Xie * big cores id is from 0-3, little cores id 4-7 1236fba6e04STony Xie * -------------------------------------------------------------------- 1246fba6e04STony Xie */ 1259ec78bdfSTony Xie add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT 1266fba6e04STony Xie /* -------------------------------------------------------------------- 1276fba6e04STony Xie * get per cpuup flag 1286fba6e04STony Xie * -------------------------------------------------------------------- 1296fba6e04STony Xie */ 1306fba6e04STony Xie adr x4, cpuson_flags 1319ec78bdfSTony Xie add x4, x4, x21, lsl #2 1326fba6e04STony Xie ldr w1, [x4] 1336fba6e04STony Xie /* -------------------------------------------------------------------- 1346fba6e04STony Xie * check cpuon reason 1356fba6e04STony Xie * -------------------------------------------------------------------- 1366fba6e04STony Xie */ 1379ec78bdfSTony Xie cmp w1, PMU_CPU_AUTO_PWRDN 1386fba6e04STony Xie b.eq boot_entry 1399ec78bdfSTony Xie cmp w1, PMU_CPU_HOTPLUG 1406fba6e04STony Xie b.eq boot_entry 1416fba6e04STony Xie /* -------------------------------------------------------------------- 1426fba6e04STony Xie * If the boot core cpuson_flags or cpuson_entry_point is not 1436fba6e04STony Xie * expection. force the core into wfe. 1446fba6e04STony Xie * -------------------------------------------------------------------- 1456fba6e04STony Xie */ 1466fba6e04STony Xiewfe_loop: 1476fba6e04STony Xie wfe 1486fba6e04STony Xie b wfe_loop 1496fba6e04STony Xieboot_entry: 1509ec78bdfSTony Xie str wzr, [x4] 151f47a25ddSCaesar Wang /* -------------------------------------------------------------------- 152f47a25ddSCaesar Wang * get per cpuup boot addr 153f47a25ddSCaesar Wang * -------------------------------------------------------------------- 154f47a25ddSCaesar Wang */ 155f47a25ddSCaesar Wang adr x5, cpuson_entry_point 1569ec78bdfSTony Xie ldr x2, [x5, x21, lsl #3] 1576fba6e04STony Xie br x2 1586fba6e04STony Xieendfunc platform_cpu_warmboot 1596fba6e04STony Xie 1606fba6e04STony Xie /* -------------------------------------------------------------------- 1616fba6e04STony Xie * Per-CPU Secure entry point - resume or power up 1626fba6e04STony Xie * -------------------------------------------------------------------- 1636fba6e04STony Xie */ 1649fd9f1d0Sshengfei Xu 1659fd9f1d0Sshengfei Xu#if USE_COHERENT_MEM 166da04341eSChris Kay .section .tzfw_coherent_mem, "a" 1679fd9f1d0Sshengfei Xu#else 1689fd9f1d0Sshengfei Xu .data 1699fd9f1d0Sshengfei Xu#endif 1706fba6e04STony Xie .align 3 1716fba6e04STony Xiecpuson_entry_point: 1726fba6e04STony Xie .rept PLATFORM_CORE_COUNT 1736fba6e04STony Xie .quad 0 1746fba6e04STony Xie .endr 1756fba6e04STony Xiecpuson_flags: 1766fba6e04STony Xie .rept PLATFORM_CORE_COUNT 177f47a25ddSCaesar Wang .word 0 1786fba6e04STony Xie .endr 1799ec78bdfSTony Xierockchip_clst_warmboot_data 180