1*82e18f89SHeiko Stuebner/* 2*82e18f89SHeiko Stuebner * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*82e18f89SHeiko Stuebner * 4*82e18f89SHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5*82e18f89SHeiko Stuebner */ 6*82e18f89SHeiko Stuebner 7*82e18f89SHeiko Stuebner#include <arch.h> 8*82e18f89SHeiko Stuebner#include <asm_macros.S> 9*82e18f89SHeiko Stuebner#include <platform_def.h> 10*82e18f89SHeiko Stuebner 11*82e18f89SHeiko Stuebner .globl pmu_cpuson_entrypoint 12*82e18f89SHeiko Stuebner .macro pmusram_entry_func _name 13*82e18f89SHeiko Stuebner .section .pmusram.entry, "ax" 14*82e18f89SHeiko Stuebner .type \_name, %function 15*82e18f89SHeiko Stuebner .cfi_startproc 16*82e18f89SHeiko Stuebner \_name: 17*82e18f89SHeiko Stuebner .endm 18*82e18f89SHeiko Stuebner 19*82e18f89SHeiko Stuebnerpmusram_entry_func pmu_cpuson_entrypoint 20*82e18f89SHeiko Stuebner 21*82e18f89SHeiko Stuebner#if PSRAM_CHECK_WAKEUP_CPU 22*82e18f89SHeiko Stuebnercheck_wake_cpus: 23*82e18f89SHeiko Stuebner ldcopr r0, MPIDR 24*82e18f89SHeiko Stuebner and r1, r0, #MPIDR_CPU_MASK 25*82e18f89SHeiko Stuebner#ifdef PLAT_RK_MPIDR_CLUSTER_MASK 26*82e18f89SHeiko Stuebner and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK 27*82e18f89SHeiko Stuebner#else 28*82e18f89SHeiko Stuebner and r0, r0, #MPIDR_CLUSTER_MASK 29*82e18f89SHeiko Stuebner#endif 30*82e18f89SHeiko Stuebner orr r0, r0, r1 31*82e18f89SHeiko Stuebner 32*82e18f89SHeiko Stuebner /* primary_cpu */ 33*82e18f89SHeiko Stuebner ldr r1, boot_mpidr 34*82e18f89SHeiko Stuebner cmp r0, r1 35*82e18f89SHeiko Stuebner beq sys_wakeup 36*82e18f89SHeiko Stuebner 37*82e18f89SHeiko Stuebner /* 38*82e18f89SHeiko Stuebner * If the core is not the primary cpu, 39*82e18f89SHeiko Stuebner * force the core into wfe. 40*82e18f89SHeiko Stuebner */ 41*82e18f89SHeiko Stuebnerwfe_loop: 42*82e18f89SHeiko Stuebner wfe 43*82e18f89SHeiko Stuebner b wfe_loop 44*82e18f89SHeiko Stuebnersys_wakeup: 45*82e18f89SHeiko Stuebner#endif 46*82e18f89SHeiko Stuebner 47*82e18f89SHeiko Stuebner#if PSRAM_DO_DDR_RESUME 48*82e18f89SHeiko Stuebnerddr_resume: 49*82e18f89SHeiko Stuebner ldr r2, =__bl32_sram_stack_end 50*82e18f89SHeiko Stuebner mov sp, r2 51*82e18f89SHeiko Stuebner bl dmc_resume 52*82e18f89SHeiko Stuebner#endif 53*82e18f89SHeiko Stuebner bl sram_restore 54*82e18f89SHeiko Stuebnersys_resume: 55*82e18f89SHeiko Stuebner bl sp_min_warm_entrypoint 56*82e18f89SHeiko Stuebnerendfunc pmu_cpuson_entrypoint 57