1*82e18f89SHeiko Stuebner/* 2*82e18f89SHeiko Stuebner * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3*82e18f89SHeiko Stuebner * 4*82e18f89SHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5*82e18f89SHeiko Stuebner */ 6*82e18f89SHeiko Stuebner 7*82e18f89SHeiko Stuebner#include <platform_def.h> 8*82e18f89SHeiko Stuebner 9*82e18f89SHeiko Stuebner#include <arch.h> 10*82e18f89SHeiko Stuebner#include <asm_macros.S> 11*82e18f89SHeiko Stuebner#include <common/bl_common.h> 12*82e18f89SHeiko Stuebner#include <cortex_a12.h> 13*82e18f89SHeiko Stuebner#include <plat_private.h> 14*82e18f89SHeiko Stuebner#include <plat_pmu_macros.S> 15*82e18f89SHeiko Stuebner 16*82e18f89SHeiko Stuebner .globl cpuson_entry_point 17*82e18f89SHeiko Stuebner .globl cpuson_flags 18*82e18f89SHeiko Stuebner .globl platform_cpu_warmboot 19*82e18f89SHeiko Stuebner .globl plat_secondary_cold_boot_setup 20*82e18f89SHeiko Stuebner .globl plat_report_exception 21*82e18f89SHeiko Stuebner .globl plat_is_my_cpu_primary 22*82e18f89SHeiko Stuebner .globl plat_my_core_pos 23*82e18f89SHeiko Stuebner .globl plat_reset_handler 24*82e18f89SHeiko Stuebner .globl plat_panic_handler 25*82e18f89SHeiko Stuebner 26*82e18f89SHeiko Stuebner /* 27*82e18f89SHeiko Stuebner * void plat_reset_handler(void); 28*82e18f89SHeiko Stuebner * 29*82e18f89SHeiko Stuebner * Determine the SOC type and call the appropriate reset 30*82e18f89SHeiko Stuebner * handler. 31*82e18f89SHeiko Stuebner * 32*82e18f89SHeiko Stuebner */ 33*82e18f89SHeiko Stuebnerfunc plat_reset_handler 34*82e18f89SHeiko Stuebner bx lr 35*82e18f89SHeiko Stuebnerendfunc plat_reset_handler 36*82e18f89SHeiko Stuebner 37*82e18f89SHeiko Stuebnerfunc plat_my_core_pos 38*82e18f89SHeiko Stuebner ldcopr r0, MPIDR 39*82e18f89SHeiko Stuebner and r1, r0, #MPIDR_CPU_MASK 40*82e18f89SHeiko Stuebner#ifdef PLAT_RK_MPIDR_CLUSTER_MASK 41*82e18f89SHeiko Stuebner and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK 42*82e18f89SHeiko Stuebner#else 43*82e18f89SHeiko Stuebner and r0, r0, #MPIDR_CLUSTER_MASK 44*82e18f89SHeiko Stuebner#endif 45*82e18f89SHeiko Stuebner add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 46*82e18f89SHeiko Stuebner bx lr 47*82e18f89SHeiko Stuebnerendfunc plat_my_core_pos 48*82e18f89SHeiko Stuebner 49*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 50*82e18f89SHeiko Stuebner * void plat_secondary_cold_boot_setup (void); 51*82e18f89SHeiko Stuebner * 52*82e18f89SHeiko Stuebner * This function performs any platform specific actions 53*82e18f89SHeiko Stuebner * needed for a secondary cpu after a cold reset e.g 54*82e18f89SHeiko Stuebner * mark the cpu's presence, mechanism to place it in a 55*82e18f89SHeiko Stuebner * holding pen etc. 56*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 57*82e18f89SHeiko Stuebner */ 58*82e18f89SHeiko Stuebnerfunc plat_secondary_cold_boot_setup 59*82e18f89SHeiko Stuebner /* rk3288 does not do cold boot for secondary CPU */ 60*82e18f89SHeiko Stuebnercb_panic: 61*82e18f89SHeiko Stuebner b cb_panic 62*82e18f89SHeiko Stuebnerendfunc plat_secondary_cold_boot_setup 63*82e18f89SHeiko Stuebner 64*82e18f89SHeiko Stuebnerfunc plat_is_my_cpu_primary 65*82e18f89SHeiko Stuebner ldcopr r0, MPIDR 66*82e18f89SHeiko Stuebner#ifdef PLAT_RK_MPIDR_CLUSTER_MASK 67*82e18f89SHeiko Stuebner ldr r1, =(PLAT_RK_MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 68*82e18f89SHeiko Stuebner#else 69*82e18f89SHeiko Stuebner ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 70*82e18f89SHeiko Stuebner#endif 71*82e18f89SHeiko Stuebner and r0, r1 72*82e18f89SHeiko Stuebner cmp r0, #PLAT_RK_PRIMARY_CPU 73*82e18f89SHeiko Stuebner moveq r0, #1 74*82e18f89SHeiko Stuebner movne r0, #0 75*82e18f89SHeiko Stuebner bx lr 76*82e18f89SHeiko Stuebnerendfunc plat_is_my_cpu_primary 77*82e18f89SHeiko Stuebner 78*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 79*82e18f89SHeiko Stuebner * void plat_panic_handler(void) 80*82e18f89SHeiko Stuebner * Call system reset function on panic. Set up an emergency stack so we 81*82e18f89SHeiko Stuebner * can run C functions (it only needs to last for a few calls until we 82*82e18f89SHeiko Stuebner * reboot anyway). 83*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 84*82e18f89SHeiko Stuebner */ 85*82e18f89SHeiko Stuebnerfunc plat_panic_handler 86*82e18f89SHeiko Stuebner bl plat_set_my_stack 87*82e18f89SHeiko Stuebner b rockchip_soc_soft_reset 88*82e18f89SHeiko Stuebnerendfunc plat_panic_handler 89*82e18f89SHeiko Stuebner 90*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 91*82e18f89SHeiko Stuebner * void platform_cpu_warmboot (void); 92*82e18f89SHeiko Stuebner * cpus online or resume entrypoint 93*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 94*82e18f89SHeiko Stuebner */ 95*82e18f89SHeiko Stuebnerfunc platform_cpu_warmboot _align=16 96*82e18f89SHeiko Stuebner push { r4 - r7, lr } 97*82e18f89SHeiko Stuebner ldcopr r0, MPIDR 98*82e18f89SHeiko Stuebner and r5, r0, #MPIDR_CPU_MASK 99*82e18f89SHeiko Stuebner#ifdef PLAT_RK_MPIDR_CLUSTER_MASK 100*82e18f89SHeiko Stuebner and r6, r0, #PLAT_RK_MPIDR_CLUSTER_MASK 101*82e18f89SHeiko Stuebner#else 102*82e18f89SHeiko Stuebner and r6, r0, #MPIDR_CLUSTER_MASK 103*82e18f89SHeiko Stuebner#endif 104*82e18f89SHeiko Stuebner mov r0, r6 105*82e18f89SHeiko Stuebner 106*82e18f89SHeiko Stuebner func_rockchip_clst_warmboot 107*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 108*82e18f89SHeiko Stuebner * big cluster id is 1 109*82e18f89SHeiko Stuebner * big cores id is from 0-3, little cores id 4-7 110*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 111*82e18f89SHeiko Stuebner */ 112*82e18f89SHeiko Stuebner add r7, r5, r6, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT 113*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 114*82e18f89SHeiko Stuebner * get per cpuup flag 115*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 116*82e18f89SHeiko Stuebner */ 117*82e18f89SHeiko Stuebner ldr r4, =cpuson_flags 118*82e18f89SHeiko Stuebner add r4, r4, r7, lsl #2 119*82e18f89SHeiko Stuebner ldr r1, [r4] 120*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 121*82e18f89SHeiko Stuebner * check cpuon reason 122*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 123*82e18f89SHeiko Stuebner */ 124*82e18f89SHeiko Stuebner cmp r1, #PMU_CPU_AUTO_PWRDN 125*82e18f89SHeiko Stuebner beq boot_entry 126*82e18f89SHeiko Stuebner cmp r1, #PMU_CPU_HOTPLUG 127*82e18f89SHeiko Stuebner beq boot_entry 128*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 129*82e18f89SHeiko Stuebner * If the boot core cpuson_flags or cpuson_entry_point is not 130*82e18f89SHeiko Stuebner * expection. force the core into wfe. 131*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 132*82e18f89SHeiko Stuebner */ 133*82e18f89SHeiko Stuebnerwfe_loop: 134*82e18f89SHeiko Stuebner wfe 135*82e18f89SHeiko Stuebner b wfe_loop 136*82e18f89SHeiko Stuebnerboot_entry: 137*82e18f89SHeiko Stuebner mov r1, #0 138*82e18f89SHeiko Stuebner str r1, [r4] 139*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 140*82e18f89SHeiko Stuebner * get per cpuup boot addr 141*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 142*82e18f89SHeiko Stuebner */ 143*82e18f89SHeiko Stuebner ldr r5, =cpuson_entry_point 144*82e18f89SHeiko Stuebner ldr r2, [r5, r7, lsl #2] /* ehem. #3 */ 145*82e18f89SHeiko Stuebner pop { r4 - r7, lr } 146*82e18f89SHeiko Stuebner 147*82e18f89SHeiko Stuebner bx r2 148*82e18f89SHeiko Stuebnerendfunc platform_cpu_warmboot 149*82e18f89SHeiko Stuebner 150*82e18f89SHeiko Stuebner /* -------------------------------------------------------------------- 151*82e18f89SHeiko Stuebner * Per-CPU Secure entry point - resume or power up 152*82e18f89SHeiko Stuebner * -------------------------------------------------------------------- 153*82e18f89SHeiko Stuebner */ 154*82e18f89SHeiko Stuebner .section tzfw_coherent_mem, "a" 155*82e18f89SHeiko Stuebner .align 3 156*82e18f89SHeiko Stuebnercpuson_entry_point: 157*82e18f89SHeiko Stuebner .rept PLATFORM_CORE_COUNT 158*82e18f89SHeiko Stuebner .quad 0 159*82e18f89SHeiko Stuebner .endr 160*82e18f89SHeiko Stuebnercpuson_flags: 161*82e18f89SHeiko Stuebner .rept PLATFORM_CORE_COUNT 162*82e18f89SHeiko Stuebner .word 0 163*82e18f89SHeiko Stuebner .endr 164*82e18f89SHeiko Stuebnerrockchip_clst_warmboot_data 165