1 /* 2 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <arch_helpers.h> 10 #include <bl1/bl1.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/console.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_storage.h> 17 #include <libfdt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_defs.h> 20 #include <platform_def.h> 21 #include <plat/common/platform.h> 22 23 #include "avs_driver.h" 24 #include "board.h" 25 #include "boot_init_dram.h" 26 #include "cpg_registers.h" 27 #include "emmc_def.h" 28 #include "emmc_hal.h" 29 #include "emmc_std.h" 30 #include "io_common.h" 31 #include "io_rcar.h" 32 #include "qos_init.h" 33 #include "rcar_def.h" 34 #include "rcar_private.h" 35 #include "rcar_version.h" 36 #include "rom_api.h" 37 38 #define MAX_DRAM_CHANNELS 4 39 /* 40 * DDR ch0 has a shadow area mapped in 32bit address space. 41 * Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space 42 * is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space. 43 */ 44 #define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL 45 46 #if RCAR_BL2_DCACHE == 1 47 /* 48 * Following symbols are only used during plat_arch_setup() only 49 * when RCAR_BL2_DCACHE is enabled. 50 */ 51 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 52 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 53 54 #if USE_COHERENT_MEM 55 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 56 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 57 #endif /* USE_COHERENT_MEM */ 58 59 #endif /* RCAR_BL2_DCACHE */ 60 61 extern void plat_rcar_gic_driver_init(void); 62 extern void plat_rcar_gic_init(void); 63 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 64 extern void bl2_system_cpg_init(void); 65 extern void bl2_secure_setting(void); 66 extern void bl2_cpg_init(void); 67 extern void rcar_io_emmc_setup(void); 68 extern void rcar_io_setup(void); 69 extern void rcar_swdt_release(void); 70 extern void rcar_swdt_init(void); 71 extern void rcar_rpc_init(void); 72 extern void rcar_dma_init(void); 73 extern void rzg_pfc_init(void); 74 75 static void bl2_init_generic_timer(void); 76 77 /* RZ/G2 product check */ 78 #if RCAR_LSI == RZ_G2M 79 #define TARGET_PRODUCT PRR_PRODUCT_M3 80 #define TARGET_NAME "RZ/G2M" 81 #elif RCAR_LSI == RZ_G2H 82 #define TARGET_PRODUCT PRR_PRODUCT_H3 83 #define TARGET_NAME "RZ/G2H" 84 #elif RCAR_LSI == RZ_G2N 85 #define TARGET_PRODUCT PRR_PRODUCT_M3N 86 #define TARGET_NAME "RZ/G2N" 87 #elif RCAR_LSI == RZ_G2E 88 #define TARGET_PRODUCT PRR_PRODUCT_E3 89 #define TARGET_NAME "RZ/G2E" 90 #elif RCAR_LSI == RCAR_AUTO 91 #define TARGET_NAME "RZ/G2M" 92 #endif /* RCAR_LSI == RZ_G2M */ 93 94 #if (RCAR_LSI == RZ_G2E) 95 #define GPIO_INDT (GPIO_INDT6) 96 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U << 13U) 97 #else 98 #define GPIO_INDT (GPIO_INDT1) 99 #define GPIO_BKUP_TRG_SHIFT (1U << 8U) 100 #endif /* RCAR_LSI == RZ_G2E */ 101 102 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 103 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 104 assert_bl31_params_do_not_fit_in_shared_memory); 105 106 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 107 108 /* FDT with DRAM configuration */ 109 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 110 static void *fdt = (void *)fdt_blob; 111 112 static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string) 113 { 114 /* Just need enough space to store 64 bit decimal integer */ 115 char num_buf[20]; 116 int i = 0; 117 unsigned int rem; 118 119 do { 120 rem = unum % radix; 121 if (rem < 0xaU) { 122 num_buf[i] = '0' + rem; 123 } else { 124 num_buf[i] = 'a' + (rem - 0xaU); 125 } 126 i++; 127 unum /= radix; 128 } while (unum > 0U); 129 130 while (--i >= 0) { 131 *string++ = num_buf[i]; 132 } 133 *string = 0; 134 } 135 136 #if RCAR_LOSSY_ENABLE == 1 137 typedef struct bl2_lossy_info { 138 uint32_t magic; 139 uint32_t a0; 140 uint32_t b0; 141 } bl2_lossy_info_t; 142 143 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 144 uint64_t end_addr, uint32_t format, 145 uint32_t enable, int fcnlnode) 146 { 147 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 148 char nodename[40] = { 0 }; 149 int ret, node; 150 151 /* Ignore undefined addresses */ 152 if (start_addr == 0UL && end_addr == 0UL) { 153 return; 154 } 155 156 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 157 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 158 159 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 160 if (ret < 0) { 161 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 162 panic(); 163 } 164 165 ret = fdt_setprop_string(fdt, node, "compatible", 166 "renesas,lossy-decompression"); 167 if (ret < 0) { 168 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n", 169 "renesas,lossy-decompression", ret); 170 panic(); 171 } 172 173 ret = fdt_appendprop_string(fdt, node, "compatible", 174 "shared-dma-pool"); 175 if (ret < 0) { 176 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n", 177 "shared-dma-pool", ret); 178 panic(); 179 } 180 181 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 182 if (ret < 0) { 183 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 184 panic(); 185 } 186 187 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 188 if (ret < 0) { 189 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 190 panic(); 191 } 192 193 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 194 if (ret < 0) { 195 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 196 panic(); 197 } 198 199 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 200 if (ret < 0) { 201 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 202 panic(); 203 } 204 } 205 206 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 207 uint64_t end_addr, uint32_t format, 208 uint32_t enable, int fcnlnode) 209 { 210 bl2_lossy_info_t info; 211 uint32_t reg; 212 213 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 214 215 reg = format | (start_addr >> 20); 216 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); 217 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20); 218 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); 219 220 info.magic = 0x12345678U; 221 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); 222 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no); 223 224 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 225 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0); 226 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0); 227 228 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 229 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), 230 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no)); 231 } 232 #endif /* RCAR_LOSSY_ENABLE == 1 */ 233 234 void bl2_plat_flush_bl31_params(void) 235 { 236 uint32_t product_cut, product, cut; 237 uint32_t boot_dev, boot_cpu; 238 uint32_t reg; 239 240 reg = mmio_read_32(RCAR_MODEMR); 241 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 242 243 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 244 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 245 emmc_terminate(); 246 } 247 248 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { 249 bl2_secure_setting(); 250 } 251 252 reg = mmio_read_32(RCAR_PRR); 253 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 254 product = reg & PRR_PRODUCT_MASK; 255 cut = reg & PRR_CUT_MASK; 256 257 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) || 258 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) { 259 /* Disable MFIS write protection */ 260 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U); 261 } 262 263 reg = mmio_read_32(RCAR_MODEMR); 264 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 265 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 266 boot_cpu == MODEMR_BOOT_CPU_CA53) { 267 if (product_cut == PRR_PRODUCT_H3_CUT20) { 268 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 269 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 270 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 271 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 272 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 273 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 274 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 275 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 276 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 277 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 278 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 279 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 280 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 281 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 282 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 283 } 284 285 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 286 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 287 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 288 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 289 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 290 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 291 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 292 293 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 294 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 295 } 296 } 297 298 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 299 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 300 301 rcar_swdt_release(); 302 bl2_system_cpg_init(); 303 304 #if RCAR_BL2_DCACHE == 1 305 /* Disable data cache (clean and invalidate) */ 306 disable_mmu_el3(); 307 #endif /* RCAR_BL2_DCACHE == 1 */ 308 } 309 310 static uint32_t is_ddr_backup_mode(void) 311 { 312 #if RCAR_SYSTEM_SUSPEND 313 static uint32_t reason = RCAR_COLD_BOOT; 314 static uint32_t once; 315 316 if (once != 0U) { 317 return reason; 318 } 319 320 once = 1; 321 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) { 322 return reason; 323 } 324 325 reason = RCAR_WARM_BOOT; 326 return reason; 327 #else /* RCAR_SYSTEM_SUSPEND */ 328 return RCAR_COLD_BOOT; 329 #endif /* RCAR_SYSTEM_SUSPEND */ 330 } 331 332 int bl2_plat_handle_pre_image_load(unsigned int image_id) 333 { 334 u_register_t *boot_kind = (void *)BOOT_KIND_BASE; 335 bl_mem_params_node_t *bl_mem_params; 336 337 if (image_id != BL31_IMAGE_ID) { 338 return 0; 339 } 340 341 bl_mem_params = get_bl_mem_params_node(image_id); 342 343 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) { 344 *boot_kind = RCAR_WARM_BOOT; 345 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 346 347 console_flush(); 348 bl2_plat_flush_bl31_params(); 349 350 /* will not return */ 351 bl2_enter_bl31(&bl_mem_params->ep_info); 352 } 353 354 *boot_kind = RCAR_COLD_BOOT; 355 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 356 357 return 0; 358 } 359 360 static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 361 { 362 uint32_t cert, len; 363 int err; 364 365 err = rcar_get_certificate(certid, &cert); 366 if (err != 0) { 367 ERROR("%s : cert file load error", __func__); 368 return 1U; 369 } 370 371 rcar_read_certificate((uint64_t)cert, &len, dest); 372 373 return 0U; 374 } 375 376 int bl2_plat_handle_post_image_load(unsigned int image_id) 377 { 378 static bl2_to_bl31_params_mem_t *params; 379 bl_mem_params_node_t *bl_mem_params; 380 uintptr_t dest; 381 uint64_t ret; 382 383 if (params == NULL) { 384 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 385 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 386 } 387 388 bl_mem_params = get_bl_mem_params_node(image_id); 389 390 switch (image_id) { 391 case BL31_IMAGE_ID: 392 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 393 &dest); 394 if (ret == 0U) { 395 bl_mem_params->image_info.image_base = dest; 396 } 397 break; 398 case BL32_IMAGE_ID: 399 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 400 &dest); 401 if (ret == 0U) { 402 bl_mem_params->image_info.image_base = dest; 403 } 404 405 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 406 sizeof(entry_point_info_t)); 407 break; 408 case BL33_IMAGE_ID: 409 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 410 sizeof(entry_point_info_t)); 411 break; 412 default: 413 break; 414 } 415 416 return 0; 417 } 418 419 struct meminfo *bl2_plat_sec_mem_layout(void) 420 { 421 return &bl2_tzram_layout; 422 } 423 424 static void bl2_populate_compatible_string(void *dt) 425 { 426 uint32_t board_type; 427 uint32_t board_rev; 428 uint32_t reg; 429 int ret; 430 431 fdt_setprop_u32(dt, 0, "#address-cells", 2); 432 fdt_setprop_u32(dt, 0, "#size-cells", 2); 433 434 /* Populate compatible string */ 435 rzg_get_board_type(&board_type, &board_rev); 436 switch (board_type) { 437 case BOARD_HIHOPE_RZ_G2M: 438 ret = fdt_setprop_string(dt, 0, "compatible", 439 "hoperun,hihope-rzg2m"); 440 break; 441 case BOARD_HIHOPE_RZ_G2H: 442 ret = fdt_setprop_string(dt, 0, "compatible", 443 "hoperun,hihope-rzg2h"); 444 break; 445 case BOARD_HIHOPE_RZ_G2N: 446 ret = fdt_setprop_string(dt, 0, "compatible", 447 "hoperun,hihope-rzg2n"); 448 break; 449 case BOARD_EK874_RZ_G2E: 450 ret = fdt_setprop_string(dt, 0, "compatible", 451 "si-linux,cat874"); 452 break; 453 default: 454 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 455 panic(); 456 break; 457 } 458 459 if (ret < 0) { 460 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 461 panic(); 462 } 463 464 reg = mmio_read_32(RCAR_PRR); 465 switch (reg & PRR_PRODUCT_MASK) { 466 case PRR_PRODUCT_M3: 467 ret = fdt_appendprop_string(dt, 0, "compatible", 468 "renesas,r8a774a1"); 469 break; 470 case PRR_PRODUCT_H3: 471 ret = fdt_appendprop_string(dt, 0, "compatible", 472 "renesas,r8a774e1"); 473 break; 474 case PRR_PRODUCT_M3N: 475 ret = fdt_appendprop_string(dt, 0, "compatible", 476 "renesas,r8a774b1"); 477 break; 478 case PRR_PRODUCT_E3: 479 ret = fdt_appendprop_string(dt, 0, "compatible", 480 "renesas,r8a774c0"); 481 break; 482 default: 483 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 484 panic(); 485 break; 486 } 487 488 if (ret < 0) { 489 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 490 panic(); 491 } 492 } 493 494 static int bl2_add_memory_node(uint64_t start, uint64_t size) 495 { 496 char nodename[32] = { 0 }; 497 uint64_t fdtsize; 498 int ret, node; 499 500 fdtsize = cpu_to_fdt64(size); 501 502 snprintf(nodename, sizeof(nodename), "memory@"); 503 unsigned_num_print(start, 16, nodename + strlen(nodename)); 504 node = ret = fdt_add_subnode(fdt, 0, nodename); 505 if (ret < 0) { 506 return ret; 507 } 508 509 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 510 if (ret < 0) { 511 return ret; 512 } 513 514 ret = fdt_setprop_u64(fdt, node, "reg", start); 515 if (ret < 0) { 516 return ret; 517 } 518 519 return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize)); 520 } 521 522 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 523 { 524 uint64_t start, size; 525 int ret, chan; 526 527 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) { 528 start = dram_config[2 * chan]; 529 size = dram_config[2 * chan + 1]; 530 if (size == 0U) { 531 continue; 532 } 533 534 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 535 chan, start, start + size - 1U, 536 (size >> 30) ? : size >> 20, 537 (size >> 30) ? "G" : "M"); 538 } 539 540 /* 541 * We add the DT nodes in reverse order here. The fdt_add_subnode() 542 * adds the DT node before the first existing DT node, so we have 543 * to add them in reverse order to get nodes sorted by address in 544 * the resulting DT. 545 */ 546 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) { 547 start = dram_config[2 * chan]; 548 size = dram_config[2 * chan + 1]; 549 if (size == 0U) { 550 continue; 551 } 552 553 /* 554 * Channel 0 is mapped in 32bit space and the first 555 * 128 MiB are reserved 556 */ 557 if (chan == 0) { 558 /* 559 * Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node 560 * for remaining region in 64 bit address space 561 */ 562 if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) { 563 start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 564 size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 565 ret = bl2_add_memory_node(start, size); 566 if (ret < 0) { 567 goto err; 568 } 569 } 570 start = 0x48000000U; 571 size -= 0x8000000U; 572 } 573 574 ret = bl2_add_memory_node(start, size); 575 if (ret < 0) { 576 goto err; 577 } 578 } 579 580 return; 581 err: 582 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 583 panic(); 584 } 585 586 static void bl2_advertise_dram_size(uint32_t product) 587 { 588 uint64_t dram_config[8] = { 589 [0] = 0x400000000ULL, 590 [2] = 0x500000000ULL, 591 [4] = 0x600000000ULL, 592 [6] = 0x700000000ULL, 593 }; 594 595 switch (product) { 596 case PRR_PRODUCT_M3: 597 /* 4GB(2GBx2 2ch split) */ 598 dram_config[1] = 0x80000000ULL; 599 dram_config[5] = 0x80000000ULL; 600 break; 601 case PRR_PRODUCT_H3: 602 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 603 /* 4GB(1GBx4) */ 604 dram_config[1] = 0x40000000ULL; 605 dram_config[3] = 0x40000000ULL; 606 dram_config[5] = 0x40000000ULL; 607 dram_config[7] = 0x40000000ULL; 608 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \ 609 (RCAR_DRAM_SPLIT == 2) 610 /* 4GB(2GBx2 2ch split) */ 611 dram_config[1] = 0x80000000ULL; 612 dram_config[3] = 0x80000000ULL; 613 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 614 /* 8GB(2GBx4: default) */ 615 dram_config[1] = 0x80000000ULL; 616 dram_config[3] = 0x80000000ULL; 617 dram_config[5] = 0x80000000ULL; 618 dram_config[7] = 0x80000000ULL; 619 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 620 break; 621 case PRR_PRODUCT_M3N: 622 /* 4GB(4GBx1) */ 623 dram_config[1] = 0x100000000ULL; 624 break; 625 case PRR_PRODUCT_E3: 626 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 627 /* 1GB(512MBx2) */ 628 dram_config[1] = 0x40000000ULL; 629 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 630 /* 2GB(512MBx4) */ 631 dram_config[1] = 0x80000000ULL; 632 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 633 /* 4GB(1GBx4) */ 634 dram_config[1] = 0x100000000ULL; 635 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 636 break; 637 default: 638 NOTICE("BL2: Detected invalid DRAM entries\n"); 639 break; 640 } 641 642 bl2_advertise_dram_entries(dram_config); 643 } 644 645 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 646 u_register_t arg3, u_register_t arg4) 647 { 648 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; 649 uint32_t product, product_cut, major, minor; 650 int32_t ret; 651 const char *str; 652 const char *unknown = "unknown"; 653 const char *cpu_ca57 = "CA57"; 654 const char *cpu_ca53 = "CA53"; 655 const char *product_g2e = "G2E"; 656 const char *product_g2h = "G2H"; 657 const char *product_g2m = "G2M"; 658 const char *product_g2n = "G2N"; 659 const char *boot_hyper80 = "HyperFlash(80MHz)"; 660 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 661 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 662 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 663 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 664 #if (RCAR_LSI == RZ_G2E) 665 uint32_t sscg; 666 const char *sscg_on = "PLL1 SSCG Clock select"; 667 const char *sscg_off = "PLL1 nonSSCG Clock select"; 668 const char *boot_hyper160 = "HyperFlash(150MHz)"; 669 #else 670 const char *boot_hyper160 = "HyperFlash(160MHz)"; 671 #endif /* RCAR_LSI == RZ_G2E */ 672 #if RZG_LCS_STATE_DETECTION_ENABLE 673 uint32_t lcs; 674 const char *lcs_secure = "SE"; 675 const char *lcs_cm = "CM"; 676 const char *lcs_dm = "DM"; 677 const char *lcs_sd = "SD"; 678 const char *lcs_fa = "FA"; 679 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 680 681 #if (RCAR_LOSSY_ENABLE == 1) 682 int fcnlnode; 683 #endif /* (RCAR_LOSSY_ENABLE == 1) */ 684 685 bl2_init_generic_timer(); 686 687 reg = mmio_read_32(RCAR_MODEMR); 688 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 689 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 690 691 bl2_cpg_init(); 692 693 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 694 boot_cpu == MODEMR_BOOT_CPU_CA53) { 695 rzg_pfc_init(); 696 rcar_console_boot_init(); 697 } 698 699 plat_rcar_gic_driver_init(); 700 plat_rcar_gic_init(); 701 rcar_swdt_init(); 702 703 /* FIQ interrupts are taken to EL3 */ 704 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 705 706 write_daifclr(DAIF_FIQ_BIT); 707 708 reg = read_midr(); 709 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 710 switch (midr) { 711 case MIDR_CA57: 712 str = cpu_ca57; 713 break; 714 case MIDR_CA53: 715 str = cpu_ca53; 716 break; 717 default: 718 str = unknown; 719 break; 720 } 721 722 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str, 723 version_of_renesas); 724 725 reg = mmio_read_32(RCAR_PRR); 726 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 727 product = reg & PRR_PRODUCT_MASK; 728 729 switch (product) { 730 case PRR_PRODUCT_M3: 731 str = product_g2m; 732 break; 733 case PRR_PRODUCT_H3: 734 str = product_g2h; 735 break; 736 case PRR_PRODUCT_M3N: 737 str = product_g2n; 738 break; 739 case PRR_PRODUCT_E3: 740 str = product_g2e; 741 break; 742 default: 743 str = unknown; 744 break; 745 } 746 747 if ((product == PRR_PRODUCT_M3) && 748 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { 749 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { 750 /* M3 Ver.1.1 or Ver.1.2 */ 751 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str); 752 } else { 753 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str, 754 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 755 } 756 } else { 757 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 758 major = major + RCAR_MAJOR_OFFSET; 759 minor = reg & RCAR_MINOR_MASK; 760 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor); 761 } 762 763 #if (RCAR_LSI == RZ_G2E) 764 if (product == PRR_PRODUCT_E3) { 765 reg = mmio_read_32(RCAR_MODEMR); 766 sscg = reg & RCAR_SSCG_MASK; 767 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 768 NOTICE("BL2: %s\n", str); 769 } 770 #endif /* RCAR_LSI == RZ_G2E */ 771 772 rzg_get_board_type(&type, &rev); 773 774 switch (type) { 775 case BOARD_HIHOPE_RZ_G2M: 776 case BOARD_HIHOPE_RZ_G2H: 777 case BOARD_HIHOPE_RZ_G2N: 778 case BOARD_EK874_RZ_G2E: 779 break; 780 default: 781 type = BOARD_UNKNOWN; 782 break; 783 } 784 785 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) { 786 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 787 } else { 788 NOTICE("BL2: Board is %s Rev.%d.%d\n", 789 GET_BOARD_NAME(type), 790 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 791 } 792 793 #if RCAR_LSI != RCAR_AUTO 794 if (product != TARGET_PRODUCT) { 795 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 796 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 797 panic(); 798 } 799 #endif /* RCAR_LSI != RCAR_AUTO */ 800 rcar_avs_init(); 801 rcar_avs_setting(); 802 803 switch (boot_dev) { 804 case MODEMR_BOOT_DEV_HYPERFLASH160: 805 str = boot_hyper160; 806 break; 807 case MODEMR_BOOT_DEV_HYPERFLASH80: 808 str = boot_hyper80; 809 break; 810 case MODEMR_BOOT_DEV_QSPI_FLASH40: 811 str = boot_qspi40; 812 break; 813 case MODEMR_BOOT_DEV_QSPI_FLASH80: 814 str = boot_qspi80; 815 break; 816 case MODEMR_BOOT_DEV_EMMC_25X1: 817 str = boot_emmc25x1; 818 break; 819 case MODEMR_BOOT_DEV_EMMC_50X8: 820 str = boot_emmc50x8; 821 break; 822 default: 823 str = unknown; 824 break; 825 } 826 NOTICE("BL2: Boot device is %s\n", str); 827 828 rcar_avs_setting(); 829 830 #if RZG_LCS_STATE_DETECTION_ENABLE 831 reg = rcar_rom_get_lcs(&lcs); 832 if (reg != 0U) { 833 str = unknown; 834 goto lcm_state; 835 } 836 837 switch (lcs) { 838 case LCS_CM: 839 str = lcs_cm; 840 break; 841 case LCS_DM: 842 str = lcs_dm; 843 break; 844 case LCS_SD: 845 str = lcs_sd; 846 break; 847 case LCS_SE: 848 str = lcs_secure; 849 break; 850 case LCS_FA: 851 str = lcs_fa; 852 break; 853 default: 854 str = unknown; 855 break; 856 } 857 858 lcm_state: 859 NOTICE("BL2: LCM state is %s\n", str); 860 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 861 862 rcar_avs_end(); 863 is_ddr_backup_mode(); 864 865 bl2_tzram_layout.total_base = BL31_BASE; 866 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 867 868 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 869 boot_cpu == MODEMR_BOOT_CPU_CA53) { 870 ret = rcar_dram_init(); 871 if (ret != 0) { 872 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 873 panic(); 874 } 875 rzg_qos_init(); 876 } 877 878 /* Set up FDT */ 879 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 880 if (ret != 0) { 881 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 882 panic(); 883 } 884 885 /* Add platform compatible string */ 886 bl2_populate_compatible_string(fdt); 887 888 /* Print DRAM layout */ 889 bl2_advertise_dram_size(product); 890 891 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 892 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 893 if (rcar_emmc_init() != EMMC_SUCCESS) { 894 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 895 panic(); 896 } 897 rcar_emmc_memcard_power(EMMC_POWER_ON); 898 if (rcar_emmc_mount() != EMMC_SUCCESS) { 899 NOTICE("BL2: Failed to eMMC mount operation.\n"); 900 panic(); 901 } 902 } else { 903 rcar_rpc_init(); 904 rcar_dma_init(); 905 } 906 907 reg = mmio_read_32(RST_WDTRSTCR); 908 reg &= ~WDTRSTCR_RWDT_RSTMSK; 909 reg |= WDTRSTCR_PASSWORD; 910 mmio_write_32(RST_WDTRSTCR, reg); 911 912 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 913 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 914 915 reg = mmio_read_32(RCAR_PRR); 916 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { 917 mmio_write_32(CPG_CA57DBGRCR, 918 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 919 } 920 921 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { 922 mmio_write_32(CPG_CA53DBGRCR, 923 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 924 } 925 926 if (product_cut == PRR_PRODUCT_H3_CUT10) { 927 reg = mmio_read_32(CPG_PLL2CR); 928 reg &= ~((uint32_t)1 << 5); 929 mmio_write_32(CPG_PLL2CR, reg); 930 931 reg = mmio_read_32(CPG_PLL4CR); 932 reg &= ~((uint32_t)1 << 5); 933 mmio_write_32(CPG_PLL4CR, reg); 934 935 reg = mmio_read_32(CPG_PLL0CR); 936 reg &= ~((uint32_t)1 << 12); 937 mmio_write_32(CPG_PLL0CR, reg); 938 } 939 #if (RCAR_LOSSY_ENABLE == 1) 940 NOTICE("BL2: Lossy Decomp areas\n"); 941 942 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 943 if (fcnlnode < 0) { 944 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 945 fcnlnode); 946 panic(); 947 } 948 949 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 950 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 951 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 952 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 953 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 954 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 955 #endif /* RCAR_LOSSY_ENABLE */ 956 957 fdt_pack(fdt); 958 NOTICE("BL2: FDT at %p\n", fdt); 959 960 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 961 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 962 rcar_io_emmc_setup(); 963 } else { 964 rcar_io_setup(); 965 } 966 } 967 968 void bl2_el3_plat_arch_setup(void) 969 { 970 #if RCAR_BL2_DCACHE == 1 971 NOTICE("BL2: D-Cache enable\n"); 972 rcar_configure_mmu_el3(BL2_BASE, 973 BL2_END - BL2_BASE, 974 BL2_RO_BASE, BL2_RO_LIMIT 975 #if USE_COHERENT_MEM 976 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 977 #endif /* USE_COHERENT_MEM */ 978 ); 979 #endif /* RCAR_BL2_DCACHE == 1 */ 980 } 981 982 void bl2_platform_setup(void) 983 { 984 /* 985 * Place holder for performing any platform initialization specific 986 * to BL2. 987 */ 988 } 989 990 static void bl2_init_generic_timer(void) 991 { 992 #if RCAR_LSI == RZ_G2E 993 uint32_t reg_cntfid = EXTAL_EBISU; 994 #else 995 uint32_t reg_cntfid; 996 uint32_t modemr; 997 uint32_t modemr_pll; 998 uint32_t pll_table[] = { 999 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1000 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1001 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1002 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1003 }; 1004 1005 modemr = mmio_read_32(RCAR_MODEMR); 1006 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1007 1008 /* Set frequency data in CNTFID0 */ 1009 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1010 #endif /* RCAR_LSI == RZ_G2E */ 1011 1012 /* Update memory mapped and register based frequency */ 1013 write_cntfrq_el0((u_register_t)reg_cntfid); 1014 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1015 /* Enable counter */ 1016 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1017 (uint32_t)CNTCR_EN); 1018 } 1019