1 /* 2 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved. 3 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <inttypes.h> 9 #include <stdint.h> 10 #include <string.h> 11 12 #include <arch_helpers.h> 13 #include <bl1/bl1.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/console.h> 18 #include <drivers/io/io_driver.h> 19 #include <drivers/io/io_storage.h> 20 #include <libfdt.h> 21 #include <lib/mmio.h> 22 #include <lib/xlat_tables/xlat_tables_defs.h> 23 #include <platform_def.h> 24 #include <plat/common/platform.h> 25 26 #include "avs_driver.h" 27 #include "board.h" 28 #include "boot_init_dram.h" 29 #include "cpg_registers.h" 30 #include "emmc_def.h" 31 #include "emmc_hal.h" 32 #include "emmc_std.h" 33 #include "io_common.h" 34 #include "io_rcar.h" 35 #include "qos_init.h" 36 #include "rcar_def.h" 37 #include "rcar_private.h" 38 #include "rcar_version.h" 39 #include "rom_api.h" 40 41 #define MAX_DRAM_CHANNELS 4 42 /* 43 * DDR ch0 has a shadow area mapped in 32bit address space. 44 * Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space 45 * is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space. 46 */ 47 #define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL 48 49 #if RCAR_BL2_DCACHE == 1 50 /* 51 * Following symbols are only used during plat_arch_setup() only 52 * when RCAR_BL2_DCACHE is enabled. 53 */ 54 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 55 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 56 57 #if USE_COHERENT_MEM 58 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 59 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 60 #endif /* USE_COHERENT_MEM */ 61 62 #endif /* RCAR_BL2_DCACHE */ 63 64 extern void plat_rcar_gic_driver_init(void); 65 extern void plat_rcar_gic_init(void); 66 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 67 extern void bl2_system_cpg_init(void); 68 extern void bl2_secure_setting(void); 69 extern void bl2_cpg_init(void); 70 extern void rcar_io_emmc_setup(void); 71 extern void rcar_io_setup(void); 72 extern void rcar_swdt_release(void); 73 extern void rcar_swdt_init(void); 74 extern void rcar_rpc_init(void); 75 extern void rcar_dma_init(void); 76 extern void rzg_pfc_init(void); 77 78 static void bl2_init_generic_timer(void); 79 80 /* RZ/G2 product check */ 81 #if RCAR_LSI == RZ_G2M 82 #define TARGET_PRODUCT PRR_PRODUCT_M3 83 #define TARGET_NAME "RZ/G2M" 84 #elif RCAR_LSI == RZ_G2H 85 #define TARGET_PRODUCT PRR_PRODUCT_H3 86 #define TARGET_NAME "RZ/G2H" 87 #elif RCAR_LSI == RZ_G2N 88 #define TARGET_PRODUCT PRR_PRODUCT_M3N 89 #define TARGET_NAME "RZ/G2N" 90 #elif RCAR_LSI == RZ_G2E 91 #define TARGET_PRODUCT PRR_PRODUCT_E3 92 #define TARGET_NAME "RZ/G2E" 93 #elif RCAR_LSI == RCAR_AUTO 94 #define TARGET_NAME "RZ/G2M" 95 #endif /* RCAR_LSI == RZ_G2M */ 96 97 #if (RCAR_LSI == RZ_G2E) 98 #define GPIO_INDT (GPIO_INDT6) 99 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U << 13U) 100 #else 101 #define GPIO_INDT (GPIO_INDT1) 102 #define GPIO_BKUP_TRG_SHIFT (1U << 8U) 103 #endif /* RCAR_LSI == RZ_G2E */ 104 105 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 106 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 107 assert_bl31_params_do_not_fit_in_shared_memory); 108 109 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 110 111 /* FDT with DRAM configuration */ 112 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 113 static void *fdt = (void *)fdt_blob; 114 115 static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string) 116 { 117 /* Just need enough space to store 64 bit decimal integer */ 118 char num_buf[20]; 119 int i = 0; 120 unsigned int rem; 121 122 do { 123 rem = unum % radix; 124 if (rem < 0xaU) { 125 num_buf[i] = '0' + rem; 126 } else { 127 num_buf[i] = 'a' + (rem - 0xaU); 128 } 129 i++; 130 unum /= radix; 131 } while (unum > 0U); 132 133 while (--i >= 0) { 134 *string++ = num_buf[i]; 135 } 136 *string = 0; 137 } 138 139 #if RCAR_LOSSY_ENABLE == 1 140 typedef struct bl2_lossy_info { 141 uint32_t magic; 142 uint32_t a0; 143 uint32_t b0; 144 } bl2_lossy_info_t; 145 146 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 147 uint64_t end_addr, uint32_t format, 148 uint32_t enable, int fcnlnode) 149 { 150 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 151 char nodename[40] = { 0 }; 152 int ret, node; 153 154 /* Ignore undefined addresses */ 155 if (start_addr == 0UL && end_addr == 0UL) { 156 return; 157 } 158 159 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 160 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 161 162 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 163 if (ret < 0) { 164 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 165 panic(); 166 } 167 168 ret = fdt_setprop_string(fdt, node, "compatible", 169 "renesas,lossy-decompression"); 170 if (ret < 0) { 171 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n", 172 "renesas,lossy-decompression", ret); 173 panic(); 174 } 175 176 ret = fdt_appendprop_string(fdt, node, "compatible", 177 "shared-dma-pool"); 178 if (ret < 0) { 179 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n", 180 "shared-dma-pool", ret); 181 panic(); 182 } 183 184 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 185 if (ret < 0) { 186 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 187 panic(); 188 } 189 190 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 191 if (ret < 0) { 192 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 193 panic(); 194 } 195 196 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 197 if (ret < 0) { 198 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 199 panic(); 200 } 201 202 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 203 if (ret < 0) { 204 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 205 panic(); 206 } 207 } 208 209 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 210 uint64_t end_addr, uint32_t format, 211 uint32_t enable, int fcnlnode) 212 { 213 bl2_lossy_info_t info; 214 uint32_t reg; 215 216 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 217 218 reg = format | (start_addr >> 20); 219 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); 220 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20); 221 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); 222 223 info.magic = 0x12345678U; 224 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); 225 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no); 226 227 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 228 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0); 229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0); 230 231 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 232 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), 233 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no)); 234 } 235 #endif /* RCAR_LOSSY_ENABLE == 1 */ 236 237 void bl2_plat_flush_bl31_params(void) 238 { 239 uint32_t product_cut, product, cut; 240 uint32_t boot_dev, boot_cpu; 241 uint32_t reg; 242 243 reg = mmio_read_32(RCAR_MODEMR); 244 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 245 246 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 247 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 248 emmc_terminate(); 249 } 250 251 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { 252 bl2_secure_setting(); 253 } 254 255 reg = mmio_read_32(RCAR_PRR); 256 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 257 product = reg & PRR_PRODUCT_MASK; 258 cut = reg & PRR_CUT_MASK; 259 260 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) || 261 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) { 262 /* Disable MFIS write protection */ 263 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U); 264 } 265 266 reg = mmio_read_32(RCAR_MODEMR); 267 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 268 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 269 boot_cpu == MODEMR_BOOT_CPU_CA53) { 270 if (product_cut == PRR_PRODUCT_H3_CUT20) { 271 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 272 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 273 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 275 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 276 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 277 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 278 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 279 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 280 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 281 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 282 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 283 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 284 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 285 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 286 } 287 288 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 289 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 290 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 291 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 292 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 293 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 294 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 295 296 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 297 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 298 } 299 } 300 301 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 302 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 303 304 rcar_swdt_release(); 305 bl2_system_cpg_init(); 306 307 #if RCAR_BL2_DCACHE == 1 308 /* Disable data cache (clean and invalidate) */ 309 disable_mmu_el3(); 310 #endif /* RCAR_BL2_DCACHE == 1 */ 311 } 312 313 static uint32_t is_ddr_backup_mode(void) 314 { 315 #if RCAR_SYSTEM_SUSPEND 316 static uint32_t reason = RCAR_COLD_BOOT; 317 static uint32_t once; 318 319 if (once != 0U) { 320 return reason; 321 } 322 323 once = 1; 324 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) { 325 return reason; 326 } 327 328 reason = RCAR_WARM_BOOT; 329 return reason; 330 #else /* RCAR_SYSTEM_SUSPEND */ 331 return RCAR_COLD_BOOT; 332 #endif /* RCAR_SYSTEM_SUSPEND */ 333 } 334 335 int bl2_plat_handle_pre_image_load(unsigned int image_id) 336 { 337 u_register_t *boot_kind = (void *)BOOT_KIND_BASE; 338 bl_mem_params_node_t *bl_mem_params; 339 340 if (image_id != BL31_IMAGE_ID) { 341 return 0; 342 } 343 344 bl_mem_params = get_bl_mem_params_node(image_id); 345 346 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) { 347 *boot_kind = RCAR_WARM_BOOT; 348 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 349 350 console_flush(); 351 bl2_plat_flush_bl31_params(); 352 353 /* will not return */ 354 bl2_enter_bl31(&bl_mem_params->ep_info); 355 } 356 357 *boot_kind = RCAR_COLD_BOOT; 358 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 359 360 return 0; 361 } 362 363 static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 364 { 365 uint32_t cert, len; 366 int err; 367 368 err = rcar_get_certificate(certid, &cert); 369 if (err != 0) { 370 ERROR("%s : cert file load error", __func__); 371 return 1U; 372 } 373 374 rcar_read_certificate((uint64_t)cert, &len, dest); 375 376 return 0U; 377 } 378 379 int bl2_plat_handle_post_image_load(unsigned int image_id) 380 { 381 static bl2_to_bl31_params_mem_t *params; 382 bl_mem_params_node_t *bl_mem_params; 383 uintptr_t dest; 384 uint64_t ret; 385 386 if (params == NULL) { 387 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 388 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 389 } 390 391 bl_mem_params = get_bl_mem_params_node(image_id); 392 393 switch (image_id) { 394 case BL31_IMAGE_ID: 395 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 396 &dest); 397 if (ret == 0U) { 398 bl_mem_params->image_info.image_base = dest; 399 } 400 break; 401 case BL32_IMAGE_ID: 402 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 403 &dest); 404 if (ret == 0U) { 405 bl_mem_params->image_info.image_base = dest; 406 } 407 408 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 409 sizeof(entry_point_info_t)); 410 break; 411 case BL33_IMAGE_ID: 412 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 413 sizeof(entry_point_info_t)); 414 break; 415 default: 416 break; 417 } 418 419 return 0; 420 } 421 422 struct meminfo *bl2_plat_sec_mem_layout(void) 423 { 424 return &bl2_tzram_layout; 425 } 426 427 static void bl2_populate_compatible_string(void *dt) 428 { 429 uint32_t board_type; 430 uint32_t board_rev; 431 uint32_t reg; 432 int ret; 433 434 fdt_setprop_u32(dt, 0, "#address-cells", 2); 435 fdt_setprop_u32(dt, 0, "#size-cells", 2); 436 437 /* Populate compatible string */ 438 rzg_get_board_type(&board_type, &board_rev); 439 switch (board_type) { 440 case BOARD_HIHOPE_RZ_G2M: 441 ret = fdt_setprop_string(dt, 0, "compatible", 442 "hoperun,hihope-rzg2m"); 443 break; 444 case BOARD_HIHOPE_RZ_G2H: 445 ret = fdt_setprop_string(dt, 0, "compatible", 446 "hoperun,hihope-rzg2h"); 447 break; 448 case BOARD_HIHOPE_RZ_G2N: 449 ret = fdt_setprop_string(dt, 0, "compatible", 450 "hoperun,hihope-rzg2n"); 451 break; 452 case BOARD_EK874_RZ_G2E: 453 ret = fdt_setprop_string(dt, 0, "compatible", 454 "si-linux,cat874"); 455 break; 456 default: 457 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 458 panic(); 459 break; 460 } 461 462 if (ret < 0) { 463 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 464 panic(); 465 } 466 467 reg = mmio_read_32(RCAR_PRR); 468 switch (reg & PRR_PRODUCT_MASK) { 469 case PRR_PRODUCT_M3: 470 ret = fdt_appendprop_string(dt, 0, "compatible", 471 "renesas,r8a774a1"); 472 break; 473 case PRR_PRODUCT_H3: 474 ret = fdt_appendprop_string(dt, 0, "compatible", 475 "renesas,r8a774e1"); 476 break; 477 case PRR_PRODUCT_M3N: 478 ret = fdt_appendprop_string(dt, 0, "compatible", 479 "renesas,r8a774b1"); 480 break; 481 case PRR_PRODUCT_E3: 482 ret = fdt_appendprop_string(dt, 0, "compatible", 483 "renesas,r8a774c0"); 484 break; 485 default: 486 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 487 panic(); 488 break; 489 } 490 491 if (ret < 0) { 492 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 493 panic(); 494 } 495 } 496 497 static int bl2_add_memory_node(uint64_t start, uint64_t size) 498 { 499 char nodename[32] = { 0 }; 500 uint64_t fdtsize; 501 int ret, node; 502 503 fdtsize = cpu_to_fdt64(size); 504 505 snprintf(nodename, sizeof(nodename), "memory@"); 506 unsigned_num_print(start, 16, nodename + strlen(nodename)); 507 node = ret = fdt_add_subnode(fdt, 0, nodename); 508 if (ret < 0) { 509 return ret; 510 } 511 512 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 513 if (ret < 0) { 514 return ret; 515 } 516 517 ret = fdt_setprop_u64(fdt, node, "reg", start); 518 if (ret < 0) { 519 return ret; 520 } 521 522 return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize)); 523 } 524 525 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 526 { 527 uint64_t start, size; 528 int ret, chan; 529 530 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) { 531 start = dram_config[2 * chan]; 532 size = dram_config[2 * chan + 1]; 533 if (size == 0U) { 534 continue; 535 } 536 537 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n", 538 chan, start, start + size - 1U, 539 (size >> 30) ? : size >> 20, 540 (size >> 30) ? "G" : "M"); 541 } 542 543 /* 544 * We add the DT nodes in reverse order here. The fdt_add_subnode() 545 * adds the DT node before the first existing DT node, so we have 546 * to add them in reverse order to get nodes sorted by address in 547 * the resulting DT. 548 */ 549 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) { 550 start = dram_config[2 * chan]; 551 size = dram_config[2 * chan + 1]; 552 if (size == 0U) { 553 continue; 554 } 555 556 /* 557 * Channel 0 is mapped in 32bit space and the first 558 * 128 MiB are reserved 559 */ 560 if (chan == 0) { 561 /* 562 * Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node 563 * for remaining region in 64 bit address space 564 */ 565 if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) { 566 start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 567 size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 568 ret = bl2_add_memory_node(start, size); 569 if (ret < 0) { 570 goto err; 571 } 572 } 573 start = 0x48000000U; 574 size -= 0x8000000U; 575 } 576 577 ret = bl2_add_memory_node(start, size); 578 if (ret < 0) { 579 goto err; 580 } 581 } 582 583 return; 584 err: 585 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 586 panic(); 587 } 588 589 static void bl2_advertise_dram_size(uint32_t product) 590 { 591 uint64_t dram_config[8] = { 592 [0] = 0x400000000ULL, 593 [2] = 0x500000000ULL, 594 [4] = 0x600000000ULL, 595 [6] = 0x700000000ULL, 596 }; 597 598 switch (product) { 599 case PRR_PRODUCT_M3: 600 /* 4GB(2GBx2 2ch split) */ 601 dram_config[1] = 0x80000000ULL; 602 dram_config[5] = 0x80000000ULL; 603 break; 604 case PRR_PRODUCT_H3: 605 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 606 /* 4GB(1GBx4) */ 607 dram_config[1] = 0x40000000ULL; 608 dram_config[3] = 0x40000000ULL; 609 dram_config[5] = 0x40000000ULL; 610 dram_config[7] = 0x40000000ULL; 611 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \ 612 (RCAR_DRAM_SPLIT == 2) 613 /* 4GB(2GBx2 2ch split) */ 614 dram_config[1] = 0x80000000ULL; 615 dram_config[3] = 0x80000000ULL; 616 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 617 /* 8GB(2GBx4: default) */ 618 dram_config[1] = 0x80000000ULL; 619 dram_config[3] = 0x80000000ULL; 620 dram_config[5] = 0x80000000ULL; 621 dram_config[7] = 0x80000000ULL; 622 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 623 break; 624 case PRR_PRODUCT_M3N: 625 /* 4GB(4GBx1) */ 626 dram_config[1] = 0x100000000ULL; 627 break; 628 case PRR_PRODUCT_E3: 629 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 630 /* 1GB(512MBx2) */ 631 dram_config[1] = 0x40000000ULL; 632 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 633 /* 2GB(512MBx4) */ 634 dram_config[1] = 0x80000000ULL; 635 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 636 /* 4GB(1GBx4) */ 637 dram_config[1] = 0x100000000ULL; 638 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 639 break; 640 default: 641 NOTICE("BL2: Detected invalid DRAM entries\n"); 642 break; 643 } 644 645 bl2_advertise_dram_entries(dram_config); 646 } 647 648 void bl2_early_platform_setup2(u_register_t arg1, u_register_t arg2, 649 u_register_t arg3, u_register_t arg4) 650 { 651 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; 652 uint32_t product, product_cut, major, minor; 653 int32_t ret; 654 const char *str; 655 const char *unknown = "unknown"; 656 const char *cpu_ca57 = "CA57"; 657 const char *cpu_ca53 = "CA53"; 658 const char *product_g2e = "G2E"; 659 const char *product_g2h = "G2H"; 660 const char *product_g2m = "G2M"; 661 const char *product_g2n = "G2N"; 662 const char *boot_hyper80 = "HyperFlash(80MHz)"; 663 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 664 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 665 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 666 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 667 #if (RCAR_LSI == RZ_G2E) 668 uint32_t sscg; 669 const char *sscg_on = "PLL1 SSCG Clock select"; 670 const char *sscg_off = "PLL1 nonSSCG Clock select"; 671 const char *boot_hyper160 = "HyperFlash(150MHz)"; 672 #else 673 const char *boot_hyper160 = "HyperFlash(160MHz)"; 674 #endif /* RCAR_LSI == RZ_G2E */ 675 #if RZG_LCS_STATE_DETECTION_ENABLE 676 uint32_t lcs; 677 const char *lcs_secure = "SE"; 678 const char *lcs_cm = "CM"; 679 const char *lcs_dm = "DM"; 680 const char *lcs_sd = "SD"; 681 const char *lcs_fa = "FA"; 682 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 683 684 #if (RCAR_LOSSY_ENABLE == 1) 685 int fcnlnode; 686 #endif /* (RCAR_LOSSY_ENABLE == 1) */ 687 688 bl2_init_generic_timer(); 689 690 reg = mmio_read_32(RCAR_MODEMR); 691 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 692 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 693 694 bl2_cpg_init(); 695 696 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 697 boot_cpu == MODEMR_BOOT_CPU_CA53) { 698 rzg_pfc_init(); 699 rcar_console_boot_init(); 700 } 701 702 plat_rcar_gic_driver_init(); 703 plat_rcar_gic_init(); 704 rcar_swdt_init(); 705 706 /* FIQ interrupts are taken to EL3 */ 707 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 708 709 write_daifclr(DAIF_FIQ_BIT); 710 711 reg = read_midr(); 712 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 713 switch (midr) { 714 case MIDR_CA57: 715 str = cpu_ca57; 716 break; 717 case MIDR_CA53: 718 str = cpu_ca53; 719 break; 720 default: 721 str = unknown; 722 break; 723 } 724 725 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str, 726 version_of_renesas); 727 728 reg = mmio_read_32(RCAR_PRR); 729 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 730 product = reg & PRR_PRODUCT_MASK; 731 732 switch (product) { 733 case PRR_PRODUCT_M3: 734 str = product_g2m; 735 break; 736 case PRR_PRODUCT_H3: 737 str = product_g2h; 738 break; 739 case PRR_PRODUCT_M3N: 740 str = product_g2n; 741 break; 742 case PRR_PRODUCT_E3: 743 str = product_g2e; 744 break; 745 default: 746 str = unknown; 747 break; 748 } 749 750 if ((product == PRR_PRODUCT_M3) && 751 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { 752 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { 753 /* M3 Ver.1.1 or Ver.1.2 */ 754 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str); 755 } else { 756 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str, 757 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 758 } 759 } else { 760 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 761 major = major + RCAR_MAJOR_OFFSET; 762 minor = reg & RCAR_MINOR_MASK; 763 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor); 764 } 765 766 #if (RCAR_LSI == RZ_G2E) 767 if (product == PRR_PRODUCT_E3) { 768 reg = mmio_read_32(RCAR_MODEMR); 769 sscg = reg & RCAR_SSCG_MASK; 770 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 771 NOTICE("BL2: %s\n", str); 772 } 773 #endif /* RCAR_LSI == RZ_G2E */ 774 775 rzg_get_board_type(&type, &rev); 776 777 switch (type) { 778 case BOARD_HIHOPE_RZ_G2M: 779 case BOARD_HIHOPE_RZ_G2H: 780 case BOARD_HIHOPE_RZ_G2N: 781 case BOARD_EK874_RZ_G2E: 782 break; 783 default: 784 type = BOARD_UNKNOWN; 785 break; 786 } 787 788 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) { 789 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 790 } else { 791 NOTICE("BL2: Board is %s Rev.%d.%d\n", 792 GET_BOARD_NAME(type), 793 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 794 } 795 796 #if RCAR_LSI != RCAR_AUTO 797 if (product != TARGET_PRODUCT) { 798 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 799 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 800 panic(); 801 } 802 #endif /* RCAR_LSI != RCAR_AUTO */ 803 rcar_avs_init(); 804 rcar_avs_setting(); 805 806 switch (boot_dev) { 807 case MODEMR_BOOT_DEV_HYPERFLASH160: 808 str = boot_hyper160; 809 break; 810 case MODEMR_BOOT_DEV_HYPERFLASH80: 811 str = boot_hyper80; 812 break; 813 case MODEMR_BOOT_DEV_QSPI_FLASH40: 814 str = boot_qspi40; 815 break; 816 case MODEMR_BOOT_DEV_QSPI_FLASH80: 817 str = boot_qspi80; 818 break; 819 case MODEMR_BOOT_DEV_EMMC_25X1: 820 str = boot_emmc25x1; 821 break; 822 case MODEMR_BOOT_DEV_EMMC_50X8: 823 str = boot_emmc50x8; 824 break; 825 default: 826 str = unknown; 827 break; 828 } 829 NOTICE("BL2: Boot device is %s\n", str); 830 831 rcar_avs_setting(); 832 833 #if RZG_LCS_STATE_DETECTION_ENABLE 834 reg = rcar_rom_get_lcs(&lcs); 835 if (reg != 0U) { 836 str = unknown; 837 goto lcm_state; 838 } 839 840 switch (lcs) { 841 case LCS_CM: 842 str = lcs_cm; 843 break; 844 case LCS_DM: 845 str = lcs_dm; 846 break; 847 case LCS_SD: 848 str = lcs_sd; 849 break; 850 case LCS_SE: 851 str = lcs_secure; 852 break; 853 case LCS_FA: 854 str = lcs_fa; 855 break; 856 default: 857 str = unknown; 858 break; 859 } 860 861 lcm_state: 862 NOTICE("BL2: LCM state is %s\n", str); 863 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 864 865 rcar_avs_end(); 866 is_ddr_backup_mode(); 867 868 bl2_tzram_layout.total_base = BL31_BASE; 869 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 870 871 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 872 boot_cpu == MODEMR_BOOT_CPU_CA53) { 873 ret = rcar_dram_init(); 874 if (ret != 0) { 875 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 876 panic(); 877 } 878 rzg_qos_init(); 879 } 880 881 /* Set up FDT */ 882 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 883 if (ret != 0) { 884 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 885 panic(); 886 } 887 888 /* Add platform compatible string */ 889 bl2_populate_compatible_string(fdt); 890 891 /* Print DRAM layout */ 892 bl2_advertise_dram_size(product); 893 894 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 895 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 896 if (rcar_emmc_init() != EMMC_SUCCESS) { 897 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 898 panic(); 899 } 900 rcar_emmc_memcard_power(EMMC_POWER_ON); 901 if (rcar_emmc_mount() != EMMC_SUCCESS) { 902 NOTICE("BL2: Failed to eMMC mount operation.\n"); 903 panic(); 904 } 905 } else { 906 rcar_rpc_init(); 907 rcar_dma_init(); 908 } 909 910 reg = mmio_read_32(RST_WDTRSTCR); 911 reg &= ~WDTRSTCR_RWDT_RSTMSK; 912 reg |= WDTRSTCR_PASSWORD; 913 mmio_write_32(RST_WDTRSTCR, reg); 914 915 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 916 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 917 918 reg = mmio_read_32(RCAR_PRR); 919 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { 920 mmio_write_32(CPG_CA57DBGRCR, 921 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 922 } 923 924 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { 925 mmio_write_32(CPG_CA53DBGRCR, 926 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 927 } 928 929 if (product_cut == PRR_PRODUCT_H3_CUT10) { 930 reg = mmio_read_32(CPG_PLL2CR); 931 reg &= ~((uint32_t)1 << 5); 932 mmio_write_32(CPG_PLL2CR, reg); 933 934 reg = mmio_read_32(CPG_PLL4CR); 935 reg &= ~((uint32_t)1 << 5); 936 mmio_write_32(CPG_PLL4CR, reg); 937 938 reg = mmio_read_32(CPG_PLL0CR); 939 reg &= ~((uint32_t)1 << 12); 940 mmio_write_32(CPG_PLL0CR, reg); 941 } 942 #if (RCAR_LOSSY_ENABLE == 1) 943 NOTICE("BL2: Lossy Decomp areas\n"); 944 945 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 946 if (fcnlnode < 0) { 947 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 948 fcnlnode); 949 panic(); 950 } 951 952 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 953 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 954 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 955 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 956 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 957 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 958 #endif /* RCAR_LOSSY_ENABLE */ 959 960 fdt_pack(fdt); 961 NOTICE("BL2: FDT at %p\n", fdt); 962 963 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 964 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 965 rcar_io_emmc_setup(); 966 } else { 967 rcar_io_setup(); 968 } 969 } 970 971 void bl2_plat_arch_setup(void) 972 { 973 #if RCAR_BL2_DCACHE == 1 974 NOTICE("BL2: D-Cache enable\n"); 975 rcar_configure_mmu_el3(BL2_BASE, 976 BL2_END - BL2_BASE, 977 BL2_RO_BASE, BL2_RO_LIMIT 978 #if USE_COHERENT_MEM 979 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 980 #endif /* USE_COHERENT_MEM */ 981 ); 982 #endif /* RCAR_BL2_DCACHE == 1 */ 983 } 984 985 void bl2_platform_setup(void) 986 { 987 /* 988 * Place holder for performing any platform initialization specific 989 * to BL2. 990 */ 991 } 992 993 static void bl2_init_generic_timer(void) 994 { 995 #if RCAR_LSI == RZ_G2E 996 uint32_t reg_cntfid = EXTAL_EBISU; 997 #else 998 uint32_t reg_cntfid; 999 uint32_t modemr; 1000 uint32_t modemr_pll; 1001 uint32_t pll_table[] = { 1002 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1003 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1004 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1005 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1006 }; 1007 1008 modemr = mmio_read_32(RCAR_MODEMR); 1009 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1010 1011 /* Set frequency data in CNTFID0 */ 1012 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1013 #endif /* RCAR_LSI == RZ_G2E */ 1014 1015 /* Update memory mapped and register based frequency */ 1016 write_cntfrq_el0((u_register_t)reg_cntfid); 1017 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1018 /* Enable counter */ 1019 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1020 (uint32_t)CNTCR_EN); 1021 } 1022