1 /* 2 * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 #include <stdint.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/console.h> 17 #include <drivers/io/io_driver.h> 18 #include <drivers/io/io_storage.h> 19 #include <libfdt.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_defs.h> 22 #include <platform_def.h> 23 #include <plat/common/platform.h> 24 25 #include "avs_driver.h" 26 #include "board.h" 27 #include "boot_init_dram.h" 28 #include "cpg_registers.h" 29 #include "emmc_def.h" 30 #include "emmc_hal.h" 31 #include "emmc_std.h" 32 #include "io_common.h" 33 #include "io_rcar.h" 34 #include "qos_init.h" 35 #include "rcar_def.h" 36 #include "rcar_private.h" 37 #include "rcar_version.h" 38 #include "rom_api.h" 39 40 #define MAX_DRAM_CHANNELS 4 41 /* 42 * DDR ch0 has a shadow area mapped in 32bit address space. 43 * Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space 44 * is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space. 45 */ 46 #define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL 47 48 #if RCAR_BL2_DCACHE == 1 49 /* 50 * Following symbols are only used during plat_arch_setup() only 51 * when RCAR_BL2_DCACHE is enabled. 52 */ 53 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 54 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 55 56 #if USE_COHERENT_MEM 57 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 58 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 59 #endif /* USE_COHERENT_MEM */ 60 61 #endif /* RCAR_BL2_DCACHE */ 62 63 extern void plat_rcar_gic_driver_init(void); 64 extern void plat_rcar_gic_init(void); 65 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 66 extern void bl2_system_cpg_init(void); 67 extern void bl2_secure_setting(void); 68 extern void bl2_cpg_init(void); 69 extern void rcar_io_emmc_setup(void); 70 extern void rcar_io_setup(void); 71 extern void rcar_swdt_release(void); 72 extern void rcar_swdt_init(void); 73 extern void rcar_rpc_init(void); 74 extern void rcar_dma_init(void); 75 extern void rzg_pfc_init(void); 76 77 static void bl2_init_generic_timer(void); 78 79 /* RZ/G2 product check */ 80 #if RCAR_LSI == RZ_G2M 81 #define TARGET_PRODUCT PRR_PRODUCT_M3 82 #define TARGET_NAME "RZ/G2M" 83 #elif RCAR_LSI == RZ_G2H 84 #define TARGET_PRODUCT PRR_PRODUCT_H3 85 #define TARGET_NAME "RZ/G2H" 86 #elif RCAR_LSI == RZ_G2N 87 #define TARGET_PRODUCT PRR_PRODUCT_M3N 88 #define TARGET_NAME "RZ/G2N" 89 #elif RCAR_LSI == RZ_G2E 90 #define TARGET_PRODUCT PRR_PRODUCT_E3 91 #define TARGET_NAME "RZ/G2E" 92 #elif RCAR_LSI == RCAR_AUTO 93 #define TARGET_NAME "RZ/G2M" 94 #endif /* RCAR_LSI == RZ_G2M */ 95 96 #if (RCAR_LSI == RZ_G2E) 97 #define GPIO_INDT (GPIO_INDT6) 98 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U << 13U) 99 #else 100 #define GPIO_INDT (GPIO_INDT1) 101 #define GPIO_BKUP_TRG_SHIFT (1U << 8U) 102 #endif /* RCAR_LSI == RZ_G2E */ 103 104 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 105 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 106 assert_bl31_params_do_not_fit_in_shared_memory); 107 108 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 109 110 /* FDT with DRAM configuration */ 111 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 112 static void *fdt = (void *)fdt_blob; 113 114 static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string) 115 { 116 /* Just need enough space to store 64 bit decimal integer */ 117 char num_buf[20]; 118 int i = 0; 119 unsigned int rem; 120 121 do { 122 rem = unum % radix; 123 if (rem < 0xaU) { 124 num_buf[i] = '0' + rem; 125 } else { 126 num_buf[i] = 'a' + (rem - 0xaU); 127 } 128 i++; 129 unum /= radix; 130 } while (unum > 0U); 131 132 while (--i >= 0) { 133 *string++ = num_buf[i]; 134 } 135 *string = 0; 136 } 137 138 #if RCAR_LOSSY_ENABLE == 1 139 typedef struct bl2_lossy_info { 140 uint32_t magic; 141 uint32_t a0; 142 uint32_t b0; 143 } bl2_lossy_info_t; 144 145 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 146 uint64_t end_addr, uint32_t format, 147 uint32_t enable, int fcnlnode) 148 { 149 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 150 char nodename[40] = { 0 }; 151 int ret, node; 152 153 /* Ignore undefined addresses */ 154 if (start_addr == 0UL && end_addr == 0UL) { 155 return; 156 } 157 158 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 159 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 160 161 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 162 if (ret < 0) { 163 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 164 panic(); 165 } 166 167 ret = fdt_setprop_string(fdt, node, "compatible", 168 "renesas,lossy-decompression"); 169 if (ret < 0) { 170 NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n", 171 "renesas,lossy-decompression", ret); 172 panic(); 173 } 174 175 ret = fdt_appendprop_string(fdt, node, "compatible", 176 "shared-dma-pool"); 177 if (ret < 0) { 178 NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n", 179 "shared-dma-pool", ret); 180 panic(); 181 } 182 183 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 184 if (ret < 0) { 185 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 186 panic(); 187 } 188 189 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 190 if (ret < 0) { 191 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 192 panic(); 193 } 194 195 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 196 if (ret < 0) { 197 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 198 panic(); 199 } 200 201 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 202 if (ret < 0) { 203 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 204 panic(); 205 } 206 } 207 208 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 209 uint64_t end_addr, uint32_t format, 210 uint32_t enable, int fcnlnode) 211 { 212 bl2_lossy_info_t info; 213 uint32_t reg; 214 215 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 216 217 reg = format | (start_addr >> 20); 218 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); 219 mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20); 220 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); 221 222 info.magic = 0x12345678U; 223 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); 224 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no); 225 226 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 227 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0); 228 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0); 229 230 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 231 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), 232 mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no)); 233 } 234 #endif /* RCAR_LOSSY_ENABLE == 1 */ 235 236 void bl2_plat_flush_bl31_params(void) 237 { 238 uint32_t product_cut, product, cut; 239 uint32_t boot_dev, boot_cpu; 240 uint32_t reg; 241 242 reg = mmio_read_32(RCAR_MODEMR); 243 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 244 245 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 246 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 247 emmc_terminate(); 248 } 249 250 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) { 251 bl2_secure_setting(); 252 } 253 254 reg = mmio_read_32(RCAR_PRR); 255 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 256 product = reg & PRR_PRODUCT_MASK; 257 cut = reg & PRR_CUT_MASK; 258 259 if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) || 260 (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) { 261 /* Disable MFIS write protection */ 262 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U); 263 } 264 265 reg = mmio_read_32(RCAR_MODEMR); 266 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 267 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 268 boot_cpu == MODEMR_BOOT_CPU_CA53) { 269 if (product_cut == PRR_PRODUCT_H3_CUT20) { 270 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 271 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 272 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 273 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 274 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 275 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 276 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 277 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 278 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 280 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 281 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 282 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 283 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 284 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 285 } 286 287 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 288 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 289 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 290 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 291 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 292 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 293 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 294 295 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 296 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 297 } 298 } 299 300 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 301 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 302 303 rcar_swdt_release(); 304 bl2_system_cpg_init(); 305 306 #if RCAR_BL2_DCACHE == 1 307 /* Disable data cache (clean and invalidate) */ 308 disable_mmu_el3(); 309 #endif /* RCAR_BL2_DCACHE == 1 */ 310 } 311 312 static uint32_t is_ddr_backup_mode(void) 313 { 314 #if RCAR_SYSTEM_SUSPEND 315 static uint32_t reason = RCAR_COLD_BOOT; 316 static uint32_t once; 317 318 if (once != 0U) { 319 return reason; 320 } 321 322 once = 1; 323 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) { 324 return reason; 325 } 326 327 reason = RCAR_WARM_BOOT; 328 return reason; 329 #else /* RCAR_SYSTEM_SUSPEND */ 330 return RCAR_COLD_BOOT; 331 #endif /* RCAR_SYSTEM_SUSPEND */ 332 } 333 334 int bl2_plat_handle_pre_image_load(unsigned int image_id) 335 { 336 u_register_t *boot_kind = (void *)BOOT_KIND_BASE; 337 bl_mem_params_node_t *bl_mem_params; 338 339 if (image_id != BL31_IMAGE_ID) { 340 return 0; 341 } 342 343 bl_mem_params = get_bl_mem_params_node(image_id); 344 345 if (is_ddr_backup_mode() != RCAR_COLD_BOOT) { 346 *boot_kind = RCAR_WARM_BOOT; 347 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 348 349 console_flush(); 350 bl2_plat_flush_bl31_params(); 351 352 /* will not return */ 353 bl2_enter_bl31(&bl_mem_params->ep_info); 354 } 355 356 *boot_kind = RCAR_COLD_BOOT; 357 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 358 359 return 0; 360 } 361 362 static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 363 { 364 uint32_t cert, len; 365 int err; 366 367 err = rcar_get_certificate(certid, &cert); 368 if (err != 0) { 369 ERROR("%s : cert file load error", __func__); 370 return 1U; 371 } 372 373 rcar_read_certificate((uint64_t)cert, &len, dest); 374 375 return 0U; 376 } 377 378 int bl2_plat_handle_post_image_load(unsigned int image_id) 379 { 380 static bl2_to_bl31_params_mem_t *params; 381 bl_mem_params_node_t *bl_mem_params; 382 uintptr_t dest; 383 uint64_t ret; 384 385 if (params == NULL) { 386 params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 387 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 388 } 389 390 bl_mem_params = get_bl_mem_params_node(image_id); 391 392 switch (image_id) { 393 case BL31_IMAGE_ID: 394 ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 395 &dest); 396 if (ret == 0U) { 397 bl_mem_params->image_info.image_base = dest; 398 } 399 break; 400 case BL32_IMAGE_ID: 401 ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 402 &dest); 403 if (ret == 0U) { 404 bl_mem_params->image_info.image_base = dest; 405 } 406 407 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 408 sizeof(entry_point_info_t)); 409 break; 410 case BL33_IMAGE_ID: 411 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 412 sizeof(entry_point_info_t)); 413 break; 414 default: 415 break; 416 } 417 418 return 0; 419 } 420 421 struct meminfo *bl2_plat_sec_mem_layout(void) 422 { 423 return &bl2_tzram_layout; 424 } 425 426 static void bl2_populate_compatible_string(void *dt) 427 { 428 uint32_t board_type; 429 uint32_t board_rev; 430 uint32_t reg; 431 int ret; 432 433 fdt_setprop_u32(dt, 0, "#address-cells", 2); 434 fdt_setprop_u32(dt, 0, "#size-cells", 2); 435 436 /* Populate compatible string */ 437 rzg_get_board_type(&board_type, &board_rev); 438 switch (board_type) { 439 case BOARD_HIHOPE_RZ_G2M: 440 ret = fdt_setprop_string(dt, 0, "compatible", 441 "hoperun,hihope-rzg2m"); 442 break; 443 case BOARD_HIHOPE_RZ_G2H: 444 ret = fdt_setprop_string(dt, 0, "compatible", 445 "hoperun,hihope-rzg2h"); 446 break; 447 case BOARD_HIHOPE_RZ_G2N: 448 ret = fdt_setprop_string(dt, 0, "compatible", 449 "hoperun,hihope-rzg2n"); 450 break; 451 case BOARD_EK874_RZ_G2E: 452 ret = fdt_setprop_string(dt, 0, "compatible", 453 "si-linux,cat874"); 454 break; 455 default: 456 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 457 panic(); 458 break; 459 } 460 461 if (ret < 0) { 462 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 463 panic(); 464 } 465 466 reg = mmio_read_32(RCAR_PRR); 467 switch (reg & PRR_PRODUCT_MASK) { 468 case PRR_PRODUCT_M3: 469 ret = fdt_appendprop_string(dt, 0, "compatible", 470 "renesas,r8a774a1"); 471 break; 472 case PRR_PRODUCT_H3: 473 ret = fdt_appendprop_string(dt, 0, "compatible", 474 "renesas,r8a774e1"); 475 break; 476 case PRR_PRODUCT_M3N: 477 ret = fdt_appendprop_string(dt, 0, "compatible", 478 "renesas,r8a774b1"); 479 break; 480 case PRR_PRODUCT_E3: 481 ret = fdt_appendprop_string(dt, 0, "compatible", 482 "renesas,r8a774c0"); 483 break; 484 default: 485 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 486 panic(); 487 break; 488 } 489 490 if (ret < 0) { 491 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 492 panic(); 493 } 494 } 495 496 static int bl2_add_memory_node(uint64_t start, uint64_t size) 497 { 498 char nodename[32] = { 0 }; 499 uint64_t fdtsize; 500 int ret, node; 501 502 fdtsize = cpu_to_fdt64(size); 503 504 snprintf(nodename, sizeof(nodename), "memory@"); 505 unsigned_num_print(start, 16, nodename + strlen(nodename)); 506 node = ret = fdt_add_subnode(fdt, 0, nodename); 507 if (ret < 0) { 508 return ret; 509 } 510 511 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 512 if (ret < 0) { 513 return ret; 514 } 515 516 ret = fdt_setprop_u64(fdt, node, "reg", start); 517 if (ret < 0) { 518 return ret; 519 } 520 521 return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize)); 522 } 523 524 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 525 { 526 uint64_t start, size; 527 int ret, chan; 528 529 for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) { 530 start = dram_config[2 * chan]; 531 size = dram_config[2 * chan + 1]; 532 if (size == 0U) { 533 continue; 534 } 535 536 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n", 537 chan, start, start + size - 1U, 538 (size >> 30) ? : size >> 20, 539 (size >> 30) ? "G" : "M"); 540 } 541 542 /* 543 * We add the DT nodes in reverse order here. The fdt_add_subnode() 544 * adds the DT node before the first existing DT node, so we have 545 * to add them in reverse order to get nodes sorted by address in 546 * the resulting DT. 547 */ 548 for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) { 549 start = dram_config[2 * chan]; 550 size = dram_config[2 * chan + 1]; 551 if (size == 0U) { 552 continue; 553 } 554 555 /* 556 * Channel 0 is mapped in 32bit space and the first 557 * 128 MiB are reserved 558 */ 559 if (chan == 0) { 560 /* 561 * Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node 562 * for remaining region in 64 bit address space 563 */ 564 if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) { 565 start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 566 size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE; 567 ret = bl2_add_memory_node(start, size); 568 if (ret < 0) { 569 goto err; 570 } 571 } 572 start = 0x48000000U; 573 size -= 0x8000000U; 574 } 575 576 ret = bl2_add_memory_node(start, size); 577 if (ret < 0) { 578 goto err; 579 } 580 } 581 582 return; 583 err: 584 NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret); 585 panic(); 586 } 587 588 static void bl2_advertise_dram_size(uint32_t product) 589 { 590 uint64_t dram_config[8] = { 591 [0] = 0x400000000ULL, 592 [2] = 0x500000000ULL, 593 [4] = 0x600000000ULL, 594 [6] = 0x700000000ULL, 595 }; 596 597 switch (product) { 598 case PRR_PRODUCT_M3: 599 /* 4GB(2GBx2 2ch split) */ 600 dram_config[1] = 0x80000000ULL; 601 dram_config[5] = 0x80000000ULL; 602 break; 603 case PRR_PRODUCT_H3: 604 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 605 /* 4GB(1GBx4) */ 606 dram_config[1] = 0x40000000ULL; 607 dram_config[3] = 0x40000000ULL; 608 dram_config[5] = 0x40000000ULL; 609 dram_config[7] = 0x40000000ULL; 610 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \ 611 (RCAR_DRAM_SPLIT == 2) 612 /* 4GB(2GBx2 2ch split) */ 613 dram_config[1] = 0x80000000ULL; 614 dram_config[3] = 0x80000000ULL; 615 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 616 /* 8GB(2GBx4: default) */ 617 dram_config[1] = 0x80000000ULL; 618 dram_config[3] = 0x80000000ULL; 619 dram_config[5] = 0x80000000ULL; 620 dram_config[7] = 0x80000000ULL; 621 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 622 break; 623 case PRR_PRODUCT_M3N: 624 /* 4GB(4GBx1) */ 625 dram_config[1] = 0x100000000ULL; 626 break; 627 case PRR_PRODUCT_E3: 628 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 629 /* 1GB(512MBx2) */ 630 dram_config[1] = 0x40000000ULL; 631 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 632 /* 2GB(512MBx4) */ 633 dram_config[1] = 0x80000000ULL; 634 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 635 /* 4GB(1GBx4) */ 636 dram_config[1] = 0x100000000ULL; 637 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 638 break; 639 default: 640 NOTICE("BL2: Detected invalid DRAM entries\n"); 641 break; 642 } 643 644 bl2_advertise_dram_entries(dram_config); 645 } 646 647 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 648 u_register_t arg3, u_register_t arg4) 649 { 650 uint32_t reg, midr, boot_dev, boot_cpu, type, rev; 651 uint32_t product, product_cut, major, minor; 652 int32_t ret; 653 const char *str; 654 const char *unknown = "unknown"; 655 const char *cpu_ca57 = "CA57"; 656 const char *cpu_ca53 = "CA53"; 657 const char *product_g2e = "G2E"; 658 const char *product_g2h = "G2H"; 659 const char *product_g2m = "G2M"; 660 const char *product_g2n = "G2N"; 661 const char *boot_hyper80 = "HyperFlash(80MHz)"; 662 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 663 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 664 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 665 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 666 #if (RCAR_LSI == RZ_G2E) 667 uint32_t sscg; 668 const char *sscg_on = "PLL1 SSCG Clock select"; 669 const char *sscg_off = "PLL1 nonSSCG Clock select"; 670 const char *boot_hyper160 = "HyperFlash(150MHz)"; 671 #else 672 const char *boot_hyper160 = "HyperFlash(160MHz)"; 673 #endif /* RCAR_LSI == RZ_G2E */ 674 #if RZG_LCS_STATE_DETECTION_ENABLE 675 uint32_t lcs; 676 const char *lcs_secure = "SE"; 677 const char *lcs_cm = "CM"; 678 const char *lcs_dm = "DM"; 679 const char *lcs_sd = "SD"; 680 const char *lcs_fa = "FA"; 681 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 682 683 #if (RCAR_LOSSY_ENABLE == 1) 684 int fcnlnode; 685 #endif /* (RCAR_LOSSY_ENABLE == 1) */ 686 687 bl2_init_generic_timer(); 688 689 reg = mmio_read_32(RCAR_MODEMR); 690 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 691 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 692 693 bl2_cpg_init(); 694 695 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 696 boot_cpu == MODEMR_BOOT_CPU_CA53) { 697 rzg_pfc_init(); 698 rcar_console_boot_init(); 699 } 700 701 plat_rcar_gic_driver_init(); 702 plat_rcar_gic_init(); 703 rcar_swdt_init(); 704 705 /* FIQ interrupts are taken to EL3 */ 706 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 707 708 write_daifclr(DAIF_FIQ_BIT); 709 710 reg = read_midr(); 711 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 712 switch (midr) { 713 case MIDR_CA57: 714 str = cpu_ca57; 715 break; 716 case MIDR_CA53: 717 str = cpu_ca53; 718 break; 719 default: 720 str = unknown; 721 break; 722 } 723 724 NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str, 725 version_of_renesas); 726 727 reg = mmio_read_32(RCAR_PRR); 728 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 729 product = reg & PRR_PRODUCT_MASK; 730 731 switch (product) { 732 case PRR_PRODUCT_M3: 733 str = product_g2m; 734 break; 735 case PRR_PRODUCT_H3: 736 str = product_g2h; 737 break; 738 case PRR_PRODUCT_M3N: 739 str = product_g2n; 740 break; 741 case PRR_PRODUCT_E3: 742 str = product_g2e; 743 break; 744 default: 745 str = unknown; 746 break; 747 } 748 749 if ((product == PRR_PRODUCT_M3) && 750 ((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) { 751 if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) { 752 /* M3 Ver.1.1 or Ver.1.2 */ 753 NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str); 754 } else { 755 NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str, 756 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 757 } 758 } else { 759 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 760 major = major + RCAR_MAJOR_OFFSET; 761 minor = reg & RCAR_MINOR_MASK; 762 NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor); 763 } 764 765 #if (RCAR_LSI == RZ_G2E) 766 if (product == PRR_PRODUCT_E3) { 767 reg = mmio_read_32(RCAR_MODEMR); 768 sscg = reg & RCAR_SSCG_MASK; 769 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 770 NOTICE("BL2: %s\n", str); 771 } 772 #endif /* RCAR_LSI == RZ_G2E */ 773 774 rzg_get_board_type(&type, &rev); 775 776 switch (type) { 777 case BOARD_HIHOPE_RZ_G2M: 778 case BOARD_HIHOPE_RZ_G2H: 779 case BOARD_HIHOPE_RZ_G2N: 780 case BOARD_EK874_RZ_G2E: 781 break; 782 default: 783 type = BOARD_UNKNOWN; 784 break; 785 } 786 787 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) { 788 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 789 } else { 790 NOTICE("BL2: Board is %s Rev.%d.%d\n", 791 GET_BOARD_NAME(type), 792 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 793 } 794 795 #if RCAR_LSI != RCAR_AUTO 796 if (product != TARGET_PRODUCT) { 797 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 798 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 799 panic(); 800 } 801 #endif /* RCAR_LSI != RCAR_AUTO */ 802 rcar_avs_init(); 803 rcar_avs_setting(); 804 805 switch (boot_dev) { 806 case MODEMR_BOOT_DEV_HYPERFLASH160: 807 str = boot_hyper160; 808 break; 809 case MODEMR_BOOT_DEV_HYPERFLASH80: 810 str = boot_hyper80; 811 break; 812 case MODEMR_BOOT_DEV_QSPI_FLASH40: 813 str = boot_qspi40; 814 break; 815 case MODEMR_BOOT_DEV_QSPI_FLASH80: 816 str = boot_qspi80; 817 break; 818 case MODEMR_BOOT_DEV_EMMC_25X1: 819 str = boot_emmc25x1; 820 break; 821 case MODEMR_BOOT_DEV_EMMC_50X8: 822 str = boot_emmc50x8; 823 break; 824 default: 825 str = unknown; 826 break; 827 } 828 NOTICE("BL2: Boot device is %s\n", str); 829 830 rcar_avs_setting(); 831 832 #if RZG_LCS_STATE_DETECTION_ENABLE 833 reg = rcar_rom_get_lcs(&lcs); 834 if (reg != 0U) { 835 str = unknown; 836 goto lcm_state; 837 } 838 839 switch (lcs) { 840 case LCS_CM: 841 str = lcs_cm; 842 break; 843 case LCS_DM: 844 str = lcs_dm; 845 break; 846 case LCS_SD: 847 str = lcs_sd; 848 break; 849 case LCS_SE: 850 str = lcs_secure; 851 break; 852 case LCS_FA: 853 str = lcs_fa; 854 break; 855 default: 856 str = unknown; 857 break; 858 } 859 860 lcm_state: 861 NOTICE("BL2: LCM state is %s\n", str); 862 #endif /* RZG_LCS_STATE_DETECTION_ENABLE */ 863 864 rcar_avs_end(); 865 is_ddr_backup_mode(); 866 867 bl2_tzram_layout.total_base = BL31_BASE; 868 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 869 870 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 871 boot_cpu == MODEMR_BOOT_CPU_CA53) { 872 ret = rcar_dram_init(); 873 if (ret != 0) { 874 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 875 panic(); 876 } 877 rzg_qos_init(); 878 } 879 880 /* Set up FDT */ 881 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 882 if (ret != 0) { 883 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 884 panic(); 885 } 886 887 /* Add platform compatible string */ 888 bl2_populate_compatible_string(fdt); 889 890 /* Print DRAM layout */ 891 bl2_advertise_dram_size(product); 892 893 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 894 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 895 if (rcar_emmc_init() != EMMC_SUCCESS) { 896 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 897 panic(); 898 } 899 rcar_emmc_memcard_power(EMMC_POWER_ON); 900 if (rcar_emmc_mount() != EMMC_SUCCESS) { 901 NOTICE("BL2: Failed to eMMC mount operation.\n"); 902 panic(); 903 } 904 } else { 905 rcar_rpc_init(); 906 rcar_dma_init(); 907 } 908 909 reg = mmio_read_32(RST_WDTRSTCR); 910 reg &= ~WDTRSTCR_RWDT_RSTMSK; 911 reg |= WDTRSTCR_PASSWORD; 912 mmio_write_32(RST_WDTRSTCR, reg); 913 914 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 915 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 916 917 reg = mmio_read_32(RCAR_PRR); 918 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) { 919 mmio_write_32(CPG_CA57DBGRCR, 920 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 921 } 922 923 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) { 924 mmio_write_32(CPG_CA53DBGRCR, 925 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 926 } 927 928 if (product_cut == PRR_PRODUCT_H3_CUT10) { 929 reg = mmio_read_32(CPG_PLL2CR); 930 reg &= ~((uint32_t)1 << 5); 931 mmio_write_32(CPG_PLL2CR, reg); 932 933 reg = mmio_read_32(CPG_PLL4CR); 934 reg &= ~((uint32_t)1 << 5); 935 mmio_write_32(CPG_PLL4CR, reg); 936 937 reg = mmio_read_32(CPG_PLL0CR); 938 reg &= ~((uint32_t)1 << 12); 939 mmio_write_32(CPG_PLL0CR, reg); 940 } 941 #if (RCAR_LOSSY_ENABLE == 1) 942 NOTICE("BL2: Lossy Decomp areas\n"); 943 944 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 945 if (fcnlnode < 0) { 946 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 947 fcnlnode); 948 panic(); 949 } 950 951 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 952 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 953 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 954 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 955 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 956 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 957 #endif /* RCAR_LOSSY_ENABLE */ 958 959 fdt_pack(fdt); 960 NOTICE("BL2: FDT at %p\n", fdt); 961 962 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 963 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 964 rcar_io_emmc_setup(); 965 } else { 966 rcar_io_setup(); 967 } 968 } 969 970 void bl2_el3_plat_arch_setup(void) 971 { 972 #if RCAR_BL2_DCACHE == 1 973 NOTICE("BL2: D-Cache enable\n"); 974 rcar_configure_mmu_el3(BL2_BASE, 975 BL2_END - BL2_BASE, 976 BL2_RO_BASE, BL2_RO_LIMIT 977 #if USE_COHERENT_MEM 978 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 979 #endif /* USE_COHERENT_MEM */ 980 ); 981 #endif /* RCAR_BL2_DCACHE == 1 */ 982 } 983 984 void bl2_platform_setup(void) 985 { 986 /* 987 * Place holder for performing any platform initialization specific 988 * to BL2. 989 */ 990 } 991 992 static void bl2_init_generic_timer(void) 993 { 994 #if RCAR_LSI == RZ_G2E 995 uint32_t reg_cntfid = EXTAL_EBISU; 996 #else 997 uint32_t reg_cntfid; 998 uint32_t modemr; 999 uint32_t modemr_pll; 1000 uint32_t pll_table[] = { 1001 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1002 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1003 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1004 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1005 }; 1006 1007 modemr = mmio_read_32(RCAR_MODEMR); 1008 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1009 1010 /* Set frequency data in CNTFID0 */ 1011 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1012 #endif /* RCAR_LSI == RZ_G2E */ 1013 1014 /* Update memory mapped and register based frequency */ 1015 write_cntfrq_el0((u_register_t)reg_cntfid); 1016 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1017 /* Enable counter */ 1018 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1019 (uint32_t)CNTCR_EN); 1020 } 1021