xref: /rk3399_ARM-atf/plat/renesas/rcar_gen5/include/rcar_private.h (revision fd2fb5b7612810ee53ab6bce74dffe955e1f252a)
1 /*
2  * Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef RCAR_PRIVATE_H
8 #define RCAR_PRIVATE_H
9 
10 #include <common/bl_common.h>
11 #include <lib/bakery_lock.h>
12 #include <lib/el3_runtime/cpu_data.h>
13 
14 #include <platform_def.h>
15 
16 typedef volatile struct mailbox {
17 	uint64_t value __aligned(CACHE_WRITEBACK_GRANULE);
18 } mailbox_t;
19 
20 /*
21  * This structure represents the superset of information that is passed to
22  * BL31 e.g. while passing control to it from BL2 which is bl31_params
23  * and bl31_plat_params and its elements
24  */
25 typedef struct bl2_to_bl31_params_mem {
26 	image_info_t bl32_image_info;
27 	image_info_t bl33_image_info;
28 	entry_point_info_t bl33_ep_info;
29 	entry_point_info_t bl32_ep_info;
30 } bl2_to_bl31_params_mem_t;
31 
32 #define RCAR_INSTANTIATE_LOCK	DEFINE_BAKERY_LOCK(rcar_lock)
33 /*
34  * Constants to specify how many bakery locks this platform implements. These
35  * are used if the platform chooses not to use coherent memory for bakery lock
36  * data structures.
37  */
38 #define RCAR_MAX_BAKERIES	2
39 
40 /*
41  * Definition of structure which holds platform specific per-cpu data. Currently
42  * it holds only the bakery lock information for each cpu. Constants to
43  * specify how many bakeries this platform implements and bakery ids are
44  * specified in rcar_def.h
45  */
46 typedef struct rcar_cpu_data {
47 	bakery_info_t pcpu_bakery_info[RCAR_MAX_BAKERIES];
48 } rcar_cpu_data_t;
49 
50 /*
51  * Helper macros for bakery lock api when using the above rcar_cpu_data_t for
52  * bakery lock data structures. It assumes that the bakery_info is at the
53  * beginning of the platform specific per-cpu data.
54  */
55 #define rcar_lock_init()	bakery_lock_init(&rcar_lock)
56 #define rcar_lock_get()		bakery_lock_get(&rcar_lock)
57 #define rcar_lock_release()	bakery_lock_release(&rcar_lock)
58 
59 /* lock for SCMI */
60 #define RCAR_SCMI_INSTANTIATE_LOCK	spinlock_t rcar_scmi_lock
61 #define RCAR_SCMI_LOCK_GET_INSTANCE	(&rcar_scmi_lock)
62 
63 /*
64  * Function and variable prototypes
65  */
66 void rcar_configure_mmu_el3(uintptr_t total_base,
67 			    size_t total_size,
68 			    uintptr_t ro_start,
69 			    uintptr_t ro_limit);
70 
71 void plat_invalidate_icache(void);
72 void plat_cci_disable(void);
73 void plat_cci_enable(void);
74 void plat_cci_init(void);
75 
76 void rcar_console_boot_init(void);
77 void rcar_console_runtime_init(void);
78 
79 void __init plat_rcar_scmi_setup(void);
80 void rcar_scmi_cpuon(u_register_t mpidr);
81 void rcar_scmi_cpuoff(const struct psci_power_state *target_state);
82 void rcar_scmi_sys_shutdown(void);
83 void rcar_scmi_sys_reboot(void);
84 void rcar_scmi_sys_suspend(void);
85 const plat_psci_ops_t *plat_rcar_psci_override_pm_ops(plat_psci_ops_t *ops);
86 
87 int32_t rcar_cluster_pos_by_mpidr(u_register_t mpidr);
88 
89 /*
90  * This mapping array has to be exported by the platform. Each element at
91  * a given index maps that core to an SCMI power domain.
92  */
93 extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[];
94 
95 #define SCMI_DOMAIN_ID_MASK		0xFFFFU
96 #define SCMI_CHANNEL_ID_MASK		0xFFFFU
97 #define SCMI_CHANNEL_ID_SHIFT		16U
98 
99 #define SET_SCMI_CHANNEL_ID(n)		\
100 	(((n) & SCMI_CHANNEL_ID_MASK) << SCMI_CHANNEL_ID_SHIFT)
101 #define SET_SCMI_DOMAIN_ID(n)		((n) & SCMI_DOMAIN_ID_MASK)
102 #define GET_SCMI_CHANNEL_ID(n)		\
103 	(((n) >> SCMI_CHANNEL_ID_SHIFT) & SCMI_CHANNEL_ID_MASK)
104 #define GET_SCMI_DOMAIN_ID(n)		((n) & SCMI_DOMAIN_ID_MASK)
105 
106 static inline unsigned int css_system_pwr_state(const psci_power_state_t *state)
107 {
108 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
109 	return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL];
110 #else
111 	return 0;
112 #endif
113 }
114 
115 #endif /* RCAR_PRIVATE_H */
116