1 /* 2 * Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RCAR_DEF_H 8 #define RCAR_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 13 #define RCAR_DOMAIN UL(0x0) 14 15 #define RCAR_TRUSTED_SRAM_BASE UL(0x8C200000) /* DRAM */ 16 #define RCAR_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256kB */ 17 #define RCAR_SHARED_MEM_BASE (RCAR_TRUSTED_SRAM_BASE + \ 18 RCAR_TRUSTED_SRAM_SIZE) 19 #define RCAR_SHARED_MEM_SIZE UL(0x00002000) /* 8kB */ 20 #define RCAR_BL31_CRASH_BASE (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE) 21 #define RCAR_BL31_CRASH_SIZE UL(0x00001000) 22 #define DEVICE_RCAR_BASE1 UL(0x10000000) 23 #define DEVICE_RCAR_SIZE1 UL(0x30000000) 24 #define DEVICE_RCAR_BASE2 UL(0xC0000000) 25 #define DEVICE_RCAR_SIZE2 UL(0x00C00000) 26 #define DEVICE_SRAM_BASE UL(0xE9042000) 27 #define DEVICE_SRAM_SIZE UL(0x00002000) 28 #define DEVICE_SRAM_DATA_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE) 29 #define DEVICE_SRAM_DATA_SIZE UL(0x00000100) 30 #define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_DATA_BASE + DEVICE_SRAM_DATA_SIZE) 31 #define DEVICE_SRAM_STACK_SIZE (UL(0x00001000) - DEVICE_SRAM_DATA_SIZE) 32 #define DEVICE_RCAR_BASE3 UL(0xE5000000) 33 #define DEVICE_RCAR_SIZE3 UL(0x1B000000) 34 /* Entrypoint mailboxes */ 35 #define MBOX_BASE RCAR_SHARED_MEM_BASE 36 #define MBOX_SIZE UL(0x800) /* 2kB: 32 cores */ 37 /* Base address where parameters to BL31 are stored */ 38 #define PARAMS_BASE (RCAR_TRUSTED_SRAM_BASE - UL(0x100000)) 39 #define PARAMS_SIZE UL(0x8000) /* 32kB */ 40 #define BOOT_KIND_BASE (PARAMS_BASE + UL(0x1700)) 41 42 /* 43 * The number of regions like RO(code), coherent and data required by 44 * different BL stages which need to be mapped in the MMU 45 */ 46 #define RCAR_BL_REGIONS 2 47 /* 48 * The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[] 49 * defined for each BL stage in platform_common.c. 50 */ 51 #define RCAR_MMAP_ENTRIES 10 52 /* BL31 */ 53 #define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE 54 55 /* CCI related constants */ 56 #define CCI500_BASE UL(0xF1200000) 57 #define CCI500_CLUSTER0_SL_IFACE_IX 0 58 #define CCI500_CLUSTER1_SL_IFACE_IX 1 59 #define CCI500_CLUSTER2_SL_IFACE_IX 2 60 #define CCI500_CLUSTER3_SL_IFACE_IX 3 61 #define RCAR_CCI_BASE CCI500_BASE 62 /* GIC */ 63 #define PLAT_ARM_GICD_BASE UL(0x39000000) /* GICD base address for View 1 */ 64 #define PLAT_ARM_GICR_BASE UL(0x38080000) 65 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 66 #define PLAT_CORE_FAULT_IRQ 17 67 /* Priority levels for ARM platforms */ 68 #if ENABLE_FEAT_RAS && FFH_SUPPORT 69 #define PLAT_RAS_PRI 0x10 70 #endif 71 72 #define ARM_IRQ_SEC_PHY_TIMER 29U 73 #define ARM_IRQ_SEC_SGI_0 8U 74 #define ARM_IRQ_SEC_SGI_1 9U 75 #define ARM_IRQ_SEC_SGI_2 10U 76 #define ARM_IRQ_SEC_SGI_3 11U 77 #define ARM_IRQ_SEC_SGI_4 12U 78 #define ARM_IRQ_SEC_SGI_5 13U 79 #define ARM_IRQ_SEC_SGI_6 14U 80 #define ARM_IRQ_SEC_SGI_7 15U 81 82 /* Timer control */ 83 #define RCAR_CNTC_BASE UL(0x1C000000) 84 #define RCAR_CNTC_EXTAL 1066666667U 85 86 /* Conversion value from seconds to micro seconds */ 87 #define RCAR_CONV_MICROSEC UL(1000000) 88 89 /* Workaround to ensure only RSIPM IPL output log firstly */ 90 #define BOOT_BASE_ADDRESS U(0x1003FC00) 91 #define BOOT_READY_CR52_FLAG U(0x01234200) 92 #define BOOT_BL31_REG (BOOT_BASE_ADDRESS + U(0x200)) 93 94 /* Memory mapped Generic timer interfaces */ 95 #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE 96 97 /* MPIDR_EL1 */ 98 #define RCAR_MPIDR_AFFMASK U(0x00FFFF00) 99 100 /* CPUPWRCTLR */ 101 #define CPUPWRCTLR_PWDN U(0x00000001) 102 103 /* For SCMI message */ 104 #define RCAR_SCMI_CHANNEL_MMU_BASE UL(0xC1060000) /* align 4kB */ 105 #define RCAR_SCMI_CHANNEL_SIZE UL(0x00001000) /* align 4kB (SCP FW defines 0x100) */ 106 #define RCAR_SCMI_CHANNEL_BASE UL(0xC1060E00) /* for A2P PSCI Command (SCP FW defines) */ 107 108 #define MFIS_SCP_COMMON_BASE UL(0x189E1000) 109 #define MFIS_MFISWACNTR_SCP (MFIS_SCP_COMMON_BASE + UL(0x00000904)) 110 #define MFISWACNTR_SCP_CODEVALUE_SET UL(0xACC00000) 111 #define MFISWACNTR_SCP_REGISTERADDRESS_MASK UL(0x000FFFFF) 112 /* MFIS CPU communication control register AP System core[k] to SCP Core(k=0-31) MFISASEICR[k=0] */ 113 #define RCAR_SCMI_MFIS_ADDR UL(0x18840004) 114 #define RCAR_SCMI_MFIS_MOD_MASK U(0x00000001) 115 #define RCAR_SCMI_MFIS_PRV_MASK (~RCAR_SCMI_MFIS_MOD_MASK) 116 117 #endif /* RCAR_DEF_H */ 118