1 /* 2 * Copyright (c) 2025, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #ifndef __ASSEMBLER__ 11 #include <stdlib.h> 12 #endif 13 14 #include <arch.h> 15 16 #include "rcar_def.h" 17 18 /******************************************************************************* 19 * Platform binary types for linking 20 ******************************************************************************/ 21 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 22 #define PLATFORM_LINKER_ARCH aarch64 23 24 /******************************************************************************* 25 * Generic platform constants 26 ******************************************************************************/ 27 28 /* Size of cacheable stacks */ 29 #define PLATFORM_STACK_SIZE 0x800U 30 31 /* 32 * R-Car X5H Cortex-A720AE 33 * L1:I/64KB per core, D/64KB per core, L2:512KB L3:4MB per cluster 34 */ 35 36 /* Hardware environment: 8 clusters, 4 cores each */ 37 #define PLATFORM_CLUSTER_COUNT 8 38 #define PLATFORM_CLUSTER0_CORE_COUNT 4 39 #define PLATFORM_CLUSTER1_CORE_COUNT 4 40 #define PLATFORM_CLUSTER2_CORE_COUNT 4 41 #define PLATFORM_CLUSTER3_CORE_COUNT 4 42 #define PLATFORM_CLUSTER4_CORE_COUNT 4 43 #define PLATFORM_CLUSTER5_CORE_COUNT 4 44 #define PLATFORM_CLUSTER6_CORE_COUNT 4 45 #define PLATFORM_CLUSTER7_CORE_COUNT 4 46 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER7_CORE_COUNT + \ 47 PLATFORM_CLUSTER6_CORE_COUNT + \ 48 PLATFORM_CLUSTER5_CORE_COUNT + \ 49 PLATFORM_CLUSTER4_CORE_COUNT + \ 50 PLATFORM_CLUSTER3_CORE_COUNT + \ 51 PLATFORM_CLUSTER2_CORE_COUNT + \ 52 PLATFORM_CLUSTER1_CORE_COUNT + \ 53 PLATFORM_CLUSTER0_CORE_COUNT) 54 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 55 56 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 57 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 58 PLATFORM_CLUSTER_COUNT + 1) 59 60 #define PLAT_MAX_RET_STATE 1 61 #define PLAT_MAX_OFF_STATE 2 62 63 /* 64 * Macros for local power states in ARM platforms encoded by State-ID field 65 * within the power-state parameter. 66 */ 67 /* Local power state for power domains in Run state. */ 68 #define ARM_LOCAL_STATE_RUN 0 69 /* Local power state for retention. Valid only for CPU power domains */ 70 #define ARM_LOCAL_STATE_RET 1 71 /* Local power state for OFF/power-down. Valid for CPU and cluster power domains */ 72 #define ARM_LOCAL_STATE_OFF 2 73 74 /* 75 ****************************************************************************** 76 * BL31 specific defines. 77 ****************************************************************************** 78 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 79 * current BL3-1 debug size plus a little space for growth. 80 */ 81 #define BL31_BASE RCAR_TRUSTED_SRAM_BASE 82 #define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + RCAR_TRUSTED_SRAM_SIZE) 83 84 /******************************************************************************* 85 * Platform specific page table and MMU setup constants 86 ******************************************************************************/ 87 #define MAX_XLAT_TABLES 8 88 89 #define PLAT_PHY_ADDR_SPACE_SIZE BIT_64(33) 90 #define PLAT_VIRT_ADDR_SPACE_SIZE BIT_64(33) 91 92 #define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS) 93 94 /******************************************************************************* 95 * Declarations and constants to access the mailboxes safely. Each mailbox is 96 * aligned on the biggest cache line size in the platform. This is known only 97 * to the platform as it might have a combination of integrated and external 98 * caches. Such alignment ensures that two mailboxes do not sit on the same cache 99 * line at any cache level. They could belong to different cpus/clusters & 100 * get written while being protected by different locks causing corruption of 101 * a valid mailbox address. 102 ******************************************************************************/ 103 #define CACHE_WRITEBACK_SHIFT 6 104 #define CACHE_WRITEBACK_GRANULE BIT(CACHE_WRITEBACK_SHIFT) 105 106 /* 107 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 108 * terminology. On a GICv2 system or mode, the lists will be merged and treated 109 * as Group 0 interrupts. 110 * 111 * PLAT_ARM_G0_IRQ_PROPS(grp) is not defined, because there are no Group 0 IRQs. 112 */ 113 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 114 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 115 GIC_INTR_CFG_LEVEL), \ 116 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 117 GIC_INTR_CFG_EDGE), \ 118 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 119 GIC_INTR_CFG_EDGE), \ 120 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 121 GIC_INTR_CFG_EDGE), \ 122 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 123 GIC_INTR_CFG_EDGE), \ 124 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 125 GIC_INTR_CFG_EDGE), \ 126 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 127 GIC_INTR_CFG_EDGE), \ 128 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 129 GIC_INTR_CFG_EDGE), \ 130 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 131 GIC_INTR_CFG_EDGE) 132 133 #endif /* PLATFORM_DEF_H */ 134