1 /* 2 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <arch_helpers.h> 10 #include <common/bl_common.h> 11 #include <common/debug.h> 12 #include <drivers/arm/cci.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/bakery_lock.h> 15 #include <lib/mmio.h> 16 #include <lib/psci/psci.h> 17 #include <plat/common/platform.h> 18 #include "pwrc.h" 19 20 #include "platform_def.h" 21 #include "rcar_def.h" 22 #include "rcar_private.h" 23 24 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 25 #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1]) 26 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0]) 27 28 static uintptr_t rcar_sec_entrypoint; 29 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT]; 30 static gicv3_dist_ctx_t dist_ctx; 31 32 static void rcar_program_mailbox(u_register_t mpidr, uintptr_t address) 33 { 34 const int linear_id = plat_core_pos_by_mpidr(mpidr); 35 void *mbox_addr = (void *)MBOX_BASE + (CACHE_WRITEBACK_GRANULE * linear_id); 36 uint64_t *value = (uint64_t *)mbox_addr; 37 38 if (linear_id < 0) { 39 ERROR("BL3-1 : The value of passed MPIDR is invalid."); 40 panic(); 41 } 42 43 *value = address; 44 45 flush_dcache_range((uintptr_t)value, CACHE_WRITEBACK_GRANULE); 46 } 47 48 static void rcar_cpu_standby(plat_local_state_t cpu_state) 49 { 50 u_register_t scr_el3 = read_scr_el3(); 51 52 write_scr_el3(scr_el3 | SCR_IRQ_BIT); 53 dsb(); 54 wfi(); 55 write_scr_el3(scr_el3); 56 } 57 58 static int rcar_pwr_domain_on(u_register_t mpidr) 59 { 60 rcar_program_mailbox(mpidr, rcar_sec_entrypoint); 61 rcar_pwrc_cpuon(mpidr); 62 63 return PSCI_E_SUCCESS; 64 } 65 66 static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state) 67 { 68 u_register_t mpidr = read_mpidr_el1(); 69 70 rcar_pwrc_disable_interrupt_wakeup(mpidr); 71 rcar_program_mailbox(mpidr, 0U); 72 } 73 74 static void rcar_pwr_domain_off(const psci_power_state_t *target_state) 75 { 76 u_register_t mpidr = read_mpidr_el1(); 77 78 rcar_pwrc_disable_interrupt_wakeup(mpidr); 79 80 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 81 rcar_pwrc_clusteroff(mpidr); 82 } else { 83 rcar_pwrc_cpuoff(mpidr); 84 } 85 } 86 87 static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state) 88 { 89 u_register_t mpidr = read_mpidr_el1(); 90 91 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) { 92 return; 93 } 94 95 rcar_program_mailbox(mpidr, rcar_sec_entrypoint); 96 rcar_pwrc_enable_interrupt_wakeup(mpidr); 97 98 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 99 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) 100 gicv3_rdistif_save(i, &rdist_ctx[i]); 101 gicv3_distif_save(&dist_ctx); 102 } 103 104 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 105 rcar_pwrc_clusteroff(mpidr); 106 } else { 107 rcar_pwrc_cpuoff(mpidr); 108 } 109 } 110 111 static void rcar_pwr_domain_suspend_finish(const psci_power_state_t 112 *target_state) 113 { 114 u_register_t mpidr = read_mpidr_el1(); 115 116 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 117 rcar_pwrc_restore_timer_state(); 118 rcar_pwrc_setup(); 119 } 120 121 rcar_pwrc_disable_interrupt_wakeup(mpidr); 122 rcar_program_mailbox(mpidr, 0U); 123 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { 124 gicv3_distif_init_restore(&dist_ctx); 125 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) 126 gicv3_rdistif_init_restore(i, &rdist_ctx[i]); 127 } 128 } 129 130 static void rcar_system_off(void) 131 { 132 u_register_t mpidr = read_mpidr_el1(); 133 uint32_t rtn_on; 134 135 if (!rcar_pwrc_mpidr_is_boot_cpu(mpidr)) 136 panic(); 137 138 rtn_on = rcar_pwrc_cpu_on_check(mpidr); 139 140 if (rtn_on > 0U) 141 panic(); 142 143 rcar_pwrc_clusteroff(mpidr); 144 } 145 146 static void rcar_system_reset(void) 147 { 148 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT(15)); 149 } 150 151 static void rcar_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 152 { 153 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) 154 rcar_pwrc_suspend_to_ram(); 155 } 156 157 static int rcar_validate_power_state(unsigned int power_state, 158 psci_power_state_t *req_state) 159 { 160 uint32_t pwr_lvl = psci_get_pstate_pwrlvl(power_state); 161 uint32_t pstate = psci_get_pstate_type(power_state); 162 uint64_t i; 163 164 if (pstate == PSTATE_TYPE_STANDBY) { 165 if (pwr_lvl != MPIDR_AFFLVL0) 166 return PSCI_E_INVALID_PARAMS; 167 168 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 169 } else { 170 for (i = MPIDR_AFFLVL0; i <= (uint64_t)pwr_lvl; i++) 171 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 172 } 173 174 if (psci_get_pstate_id(power_state) != 0U) 175 return PSCI_E_INVALID_PARAMS; 176 177 return PSCI_E_SUCCESS; 178 } 179 180 static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state) 181 { 182 uint64_t i; 183 u_register_t mpidr = read_mpidr_el1(); 184 185 if (!rcar_pwrc_mpidr_is_boot_cpu(mpidr)) { 186 /* deny system suspend entry */ 187 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 188 PSCI_LOCAL_STATE_RUN; 189 190 for (i = MPIDR_AFFLVL0; i < (uint64_t)PLAT_MAX_PWR_LVL; i++) 191 req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE; 192 } else { 193 for (i = MPIDR_AFFLVL0; i <= (uint64_t)PLAT_MAX_PWR_LVL; i++) 194 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 195 } 196 } 197 198 static plat_psci_ops_t rcar_plat_psci_ops = { 199 .cpu_standby = rcar_cpu_standby, 200 .pwr_domain_on = rcar_pwr_domain_on, 201 .pwr_domain_off = rcar_pwr_domain_off, 202 .pwr_domain_suspend = rcar_pwr_domain_suspend, 203 .pwr_domain_on_finish = rcar_pwr_domain_on_finish, 204 .pwr_domain_suspend_finish = rcar_pwr_domain_suspend_finish, 205 .system_off = rcar_system_off, 206 .system_reset = rcar_system_reset, 207 .validate_power_state = rcar_validate_power_state, 208 .pwr_domain_pwr_down = rcar_pwr_domain_pwr_down_wfi, 209 .get_sys_suspend_power_state = rcar_get_sys_suspend_power_state, 210 }; 211 212 int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) 213 { 214 *psci_ops = &rcar_plat_psci_ops; 215 rcar_sec_entrypoint = sec_entrypoint; 216 217 return 0; 218 } 219