1 /* 2 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef RCAR_DEF_H 8 #define RCAR_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 13 #define RCAR_DOMAIN UL(0x0) 14 15 #define RCAR_TRUSTED_SRAM_BASE UL(0x46400000) 16 #define RCAR_TRUSTED_SRAM_SIZE UL(0x00022000) 17 #define RCAR_SHARED_MEM_BASE (RCAR_TRUSTED_SRAM_BASE + \ 18 RCAR_TRUSTED_SRAM_SIZE) 19 #define RCAR_SHARED_MEM_SIZE UL(0x00001000) 20 #define RCAR_BL31_CRASH_BASE (RCAR_TRUSTED_SRAM_BASE + UL(0x3F000)) 21 #define RCAR_BL31_CRASH_SIZE UL(0x00001000) 22 #define DEVICE_RCAR_BASE UL(0xE6000000) 23 #define DEVICE_RCAR_SIZE UL(0x00300000) 24 #define DEVICE_SRAM_BASE UL(0xE6342000) 25 #define DEVICE_SRAM_SIZE UL(0x00002000) 26 #define DEVICE_SRAM_DATA_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE) 27 #define DEVICE_SRAM_DATA_SIZE UL(0x00000100) 28 #define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_DATA_BASE + DEVICE_SRAM_DATA_SIZE) 29 #define DEVICE_SRAM_STACK_SIZE (UL(0x00001000) - DEVICE_SRAM_DATA_SIZE) 30 #define DEVICE_RCAR_BASE2 UL(0xE6370000) 31 #define DEVICE_RCAR_SIZE2 UL(0x19C90000) 32 /* Entrypoint mailboxes */ 33 #define MBOX_BASE RCAR_SHARED_MEM_BASE 34 #define MBOX_SIZE UL(0x200) 35 /* Base address where parameters to BL31 are stored */ 36 #define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) 37 #define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \ 38 RCAR_SHARED_MEM_SIZE - UL(0x100)) 39 /* 40 * The number of regions like RO(code), coherent and data required by 41 * different BL stages which need to be mapped in the MMU 42 */ 43 #define RCAR_BL_REGIONS 2 44 /* 45 * The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[] 46 * defined for each BL stage in platform_common.c. 47 */ 48 #define RCAR_MMAP_ENTRIES 8 49 /* BL31 */ 50 #define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE 51 52 /* CCI related constants */ 53 #define CCI500_BASE UL(0xF1200000) 54 #define CCI500_CLUSTER0_SL_IFACE_IX 0 55 #define CCI500_CLUSTER1_SL_IFACE_IX 1 56 #define CCI500_CLUSTER2_SL_IFACE_IX 2 57 #define CCI500_CLUSTER3_SL_IFACE_IX 3 58 #define RCAR_CCI_BASE CCI500_BASE 59 60 /* APSREG boot configuration */ 61 #define APSREG_BASE UL(0xE6280000) 62 #define APSREG_CCI500_AUX (APSREG_BASE + UL(0x9010)) 63 #define APSREG_P_CCI500_AUX (APSREG_BASE + UL(0x29010)) 64 65 #define APSREG_AP_CLUSTER_AUX0_INIT 0x00000003U 66 #define APSREG_CCI500_AUX_INIT 0x00000001U 67 #define APSREG_P_CCI500_AUX_INIT 0x00000002U 68 69 /* GIC */ 70 #define PLAT_ARM_GICD_BASE UL(0xF1000000) 71 #define PLAT_ARM_GICR_BASE UL(0xF1060000) 72 #define ARM_IRQ_SEC_PHY_TIMER 29U 73 #define ARM_IRQ_SEC_SGI_0 8U 74 #define ARM_IRQ_SEC_SGI_1 9U 75 #define ARM_IRQ_SEC_SGI_2 10U 76 #define ARM_IRQ_SEC_SGI_3 11U 77 #define ARM_IRQ_SEC_SGI_4 12U 78 #define ARM_IRQ_SEC_SGI_5 13U 79 #define ARM_IRQ_SEC_SGI_6 14U 80 #define ARM_IRQ_SEC_SGI_7 15U 81 82 /* Timer control */ 83 #define RCAR_CNTC_BASE UL(0xE6080000) 84 #if (RCAR_LSI == RCAR_S4) 85 #define RCAR_CNTC_EXTAL 16666666U 86 #elif (RCAR_LSI == RCAR_V4H) 87 #define RCAR_CNTC_EXTAL 16666600U 88 #elif (RCAR_LSI == RCAR_V4M) 89 #define RCAR_CNTC_EXTAL 16666600U 90 #endif 91 /* Counter Count Value Lower register */ 92 #define RCAR_CNTCVL_OFF UL(0x008) 93 /* Counter Count Value Upper register */ 94 #define RCAR_CNTCVU_OFF UL(0x00C) 95 /* Conversion value from seconds to micro seconds */ 96 #define RCAR_CONV_MICROSEC 1000000UL 97 98 /* APMU */ 99 #define RCAR_APMU_BASE (UL(0xE6170000) + (RCAR_DOMAIN * UL(0x1000))) 100 #define RCAR_APMU_PWRCTRLCL_PCHPDNEN BIT(17) 101 102 #define RCAR_APMU_PWRCTRLC_WUP_REQ BIT(0) 103 #define RCAR_APMU_PWRCTRLC_IWUP_EN BIT(4) 104 #define RCAR_APMU_PWRCTRLC_PCHPDNEN BIT(17) 105 106 #define RCAR_APMU_SAFECTRLC_DBGGEN BIT(13) 107 108 #define RCAR_APMU_FSMSTSRC_STATE_OFF 0x00000000U 109 110 #define RCAR_APMU_RVBARPLC_MASK 0xFFFFFFFCU 111 #define RCAR_APMU_RVBARPL_VLD 0x00000001U 112 113 /* Soft Power On Reset Control Register 0 */ 114 #define RCAR_SRESCR (UL(0xE6160018) + (RCAR_DOMAIN * UL(0x4000))) 115 116 /* Product register */ 117 #define RCAR_PRR UL(0xFFF00044) 118 #define RCAR_CPU_HAVE_CAXX 0x00000000U 119 #define PRR_CAXX_XX_EN_CLUSTER_MASK 0x00000004U 120 121 /* Memory mapped Generic timer interfaces */ 122 #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE 123 124 /* MPIDR_EL1 */ 125 #define RCAR_MPIDR_AFFMASK 0x00FFFF00U 126 127 /* CPUPWRCTLR */ 128 #define CPUPWRCTLR_PWDN 0x00000001U 129 130 /* For DDR self refresh */ 131 #define DBSC4_REG_BASE UL(0xE6790000) 132 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + UL(0x0100)) 133 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + UL(0x0200)) 134 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + UL(0x0204)) 135 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + UL(0x0208)) 136 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + UL(0x0210)) 137 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + UL(0x0424)) 138 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + UL(0x0520)) 139 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + UL(0x0940)) 140 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + UL(0x0980)) 141 142 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE 0x00001234U 143 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE 0x00000000U 144 #define DBSC4_SET_DBCMD_OPC_PRE 0x04000000U 145 #define DBSC4_SET_DBCMD_OPC_SR 0x0A000000U 146 #define DBSC4_SET_DBCMD_OPC_MRW 0x0E000000U 147 #define DBSC4_SET_DBCMD_OPC_PD 0x08000000U 148 #define DBSC4_SET_DBCMD_CH_ALL 0x00800000U 149 #define DBSC4_SET_DBCMD_RANK_ALL 0x00040000U 150 #define DBSC4_SET_DBCMD_ARG_ALL 0x00000010U 151 #define DBSC4_SET_DBCMD_ARG_ENTER 0x00000000U 152 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC 0x00000B00U 153 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN 0x00000001U 154 #define DBSC4_BIT_DBCAM0STAT0 0x00000001U 155 #define RCAR_WAIT_DBCS4_FLUSH 50UL 156 157 #endif /* RCAR_DEF_H */ 158