1 /* 2 * Copyright (c) 2018-2023, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <inttypes.h> 8 #include <stdint.h> 9 #include <string.h> 10 11 #include <libfdt.h> 12 13 #include <platform_def.h> 14 15 #include <arch_helpers.h> 16 #include <bl1/bl1.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <common/desc_image_load.h> 20 #include <common/image_decompress.h> 21 #include <drivers/console.h> 22 #include <drivers/io/io_driver.h> 23 #include <drivers/io/io_storage.h> 24 #include <lib/mmio.h> 25 #include <lib/xlat_tables/xlat_tables_defs.h> 26 #include <plat/common/platform.h> 27 #if RCAR_GEN3_BL33_GZIP == 1 28 #include <tf_gunzip.h> 29 #endif 30 31 #include "avs_driver.h" 32 #include "boot_init_dram.h" 33 #include "cpg_registers.h" 34 #include "board.h" 35 #include "emmc_def.h" 36 #include "emmc_hal.h" 37 #include "emmc_std.h" 38 39 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 40 #include "iic_dvfs.h" 41 #endif 42 43 #include "io_common.h" 44 #include "io_rcar.h" 45 #include "qos_init.h" 46 #include "rcar_def.h" 47 #include "rcar_private.h" 48 #include "rcar_version.h" 49 #include "rom_api.h" 50 51 #if RCAR_BL2_DCACHE == 1 52 /* 53 * Following symbols are only used during plat_arch_setup() only 54 * when RCAR_BL2_DCACHE is enabled. 55 */ 56 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 57 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 58 59 #if USE_COHERENT_MEM 60 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 61 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 62 #endif 63 64 #endif 65 66 extern void plat_rcar_gic_driver_init(void); 67 extern void plat_rcar_gic_init(void); 68 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 69 extern void bl2_system_cpg_init(void); 70 extern void bl2_secure_setting(void); 71 extern void bl2_ram_security_setting_finish(void); 72 extern void bl2_cpg_init(void); 73 extern void rcar_io_emmc_setup(void); 74 extern void rcar_io_setup(void); 75 extern void rcar_swdt_release(void); 76 extern void rcar_swdt_init(void); 77 extern void rcar_rpc_init(void); 78 extern void rcar_pfc_init(void); 79 extern void rcar_dma_init(void); 80 81 static void bl2_init_generic_timer(void); 82 83 /* R-Car Gen3 product check */ 84 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 85 #define TARGET_PRODUCT PRR_PRODUCT_H3 86 #define TARGET_NAME "R-Car H3" 87 #elif RCAR_LSI == RCAR_M3 88 #define TARGET_PRODUCT PRR_PRODUCT_M3 89 #define TARGET_NAME "R-Car M3" 90 #elif RCAR_LSI == RCAR_M3N 91 #define TARGET_PRODUCT PRR_PRODUCT_M3N 92 #define TARGET_NAME "R-Car M3N" 93 #elif RCAR_LSI == RCAR_V3M 94 #define TARGET_PRODUCT PRR_PRODUCT_V3M 95 #define TARGET_NAME "R-Car V3M" 96 #elif RCAR_LSI == RCAR_E3 97 #define TARGET_PRODUCT PRR_PRODUCT_E3 98 #define TARGET_NAME "R-Car E3" 99 #elif RCAR_LSI == RCAR_D3 100 #define TARGET_PRODUCT PRR_PRODUCT_D3 101 #define TARGET_NAME "R-Car D3" 102 #elif RCAR_LSI == RCAR_AUTO 103 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 104 #endif 105 106 #if (RCAR_LSI == RCAR_E3) 107 #define GPIO_INDT (GPIO_INDT6) 108 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 109 #else 110 #define GPIO_INDT (GPIO_INDT1) 111 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 112 #endif 113 114 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 115 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 116 assert_bl31_params_do_not_fit_in_shared_memory); 117 118 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 119 120 /* FDT with DRAM configuration */ 121 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 122 static void *fdt = (void *)fdt_blob; 123 124 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 125 char *string) 126 { 127 /* Just need enough space to store 64 bit decimal integer */ 128 char num_buf[20]; 129 int i = 0; 130 unsigned int rem; 131 132 do { 133 rem = unum % radix; 134 if (rem < 0xa) 135 num_buf[i] = '0' + rem; 136 else 137 num_buf[i] = 'a' + (rem - 0xa); 138 i++; 139 unum /= radix; 140 } while (unum > 0U); 141 142 while (--i >= 0) 143 *string++ = num_buf[i]; 144 *string = 0; 145 } 146 147 #if (RCAR_LOSSY_ENABLE == 1) 148 typedef struct bl2_lossy_info { 149 uint32_t magic; 150 uint32_t a0; 151 uint32_t b0; 152 } bl2_lossy_info_t; 153 154 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 155 uint64_t end_addr, uint32_t format, 156 uint32_t enable, int fcnlnode) 157 { 158 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 159 char nodename[40] = { 0 }; 160 int ret, node; 161 162 /* Ignore undefined addresses */ 163 if (start_addr == 0 && end_addr == 0) 164 return; 165 166 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 167 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 168 169 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 170 if (ret < 0) { 171 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 172 panic(); 173 } 174 175 ret = fdt_setprop_string(fdt, node, "compatible", 176 "renesas,lossy-decompression"); 177 if (ret < 0) { 178 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 179 panic(); 180 } 181 182 ret = fdt_appendprop_string(fdt, node, "compatible", 183 "shared-dma-pool"); 184 if (ret < 0) { 185 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 186 panic(); 187 } 188 189 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 190 if (ret < 0) { 191 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 192 panic(); 193 } 194 195 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 196 if (ret < 0) { 197 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 198 panic(); 199 } 200 201 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 202 if (ret < 0) { 203 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 204 panic(); 205 } 206 207 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 208 if (ret < 0) { 209 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 210 panic(); 211 } 212 } 213 214 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 215 uint64_t end_addr, uint32_t format, 216 uint32_t enable, int fcnlnode) 217 { 218 bl2_lossy_info_t info; 219 uint32_t reg; 220 221 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 222 223 reg = format | (start_addr >> 20); 224 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 225 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 226 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 227 228 info.magic = 0x12345678U; 229 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 230 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 231 232 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 233 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 234 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 235 236 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 237 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 238 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 239 } 240 241 static int bl2_create_reserved_memory(void) 242 { 243 int ret; 244 245 int fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 246 if (fcnlnode < 0) { 247 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 248 fcnlnode); 249 panic(); 250 } 251 252 ret = fdt_setprop(fdt, fcnlnode, "ranges", NULL, 0); 253 if (ret < 0) { 254 NOTICE("BL2: Cannot add FCNL ranges prop (ret=%i)\n", ret); 255 panic(); 256 } 257 258 ret = fdt_setprop_u32(fdt, fcnlnode, "#address-cells", 2); 259 if (ret < 0) { 260 NOTICE("BL2: Cannot add FCNL #address-cells prop (ret=%i)\n", ret); 261 panic(); 262 } 263 264 ret = fdt_setprop_u32(fdt, fcnlnode, "#size-cells", 2); 265 if (ret < 0) { 266 NOTICE("BL2: Cannot add FCNL #size-cells prop (ret=%i)\n", ret); 267 panic(); 268 } 269 270 return fcnlnode; 271 } 272 273 static void bl2_create_fcnl_reserved_memory(void) 274 { 275 int fcnlnode; 276 277 NOTICE("BL2: Lossy Decomp areas\n"); 278 279 fcnlnode = bl2_create_reserved_memory(); 280 281 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 282 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 283 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 284 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 285 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 286 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 287 } 288 #else 289 static void bl2_create_fcnl_reserved_memory(void) {} 290 #endif 291 292 void bl2_plat_flush_bl31_params(void) 293 { 294 uint32_t product_cut, product, cut; 295 uint32_t boot_dev, boot_cpu; 296 uint32_t lcs, reg, val; 297 298 reg = mmio_read_32(RCAR_MODEMR); 299 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 300 301 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 302 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 303 emmc_terminate(); 304 305 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 306 bl2_secure_setting(); 307 308 reg = mmio_read_32(RCAR_PRR); 309 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 310 product = reg & PRR_PRODUCT_MASK; 311 cut = reg & PRR_CUT_MASK; 312 313 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 314 goto tlb; 315 316 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 317 goto tlb; 318 319 /* Disable MFIS write protection */ 320 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 321 322 tlb: 323 reg = mmio_read_32(RCAR_MODEMR); 324 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 325 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 326 boot_cpu != MODEMR_BOOT_CPU_CA53) 327 goto mmu; 328 329 if (product_cut == PRR_PRODUCT_H3_CUT20) { 330 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 331 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 332 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 333 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 334 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 335 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 336 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 337 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 338 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 339 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 340 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 341 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 342 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 343 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 344 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 345 } 346 347 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 348 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 349 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 350 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 351 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 352 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 353 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 354 355 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 356 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 357 } 358 359 mmu: 360 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 361 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 362 363 val = rcar_rom_get_lcs(&lcs); 364 if (val) { 365 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 366 panic(); 367 } 368 369 if (lcs == LCS_SE) 370 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 371 372 rcar_swdt_release(); 373 bl2_system_cpg_init(); 374 375 #if RCAR_BL2_DCACHE == 1 376 /* Disable data cache (clean and invalidate) */ 377 disable_mmu_el3(); 378 #endif 379 } 380 381 static uint32_t is_ddr_backup_mode(void) 382 { 383 #if RCAR_SYSTEM_SUSPEND 384 static uint32_t reason = RCAR_COLD_BOOT; 385 static uint32_t once; 386 387 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 388 uint8_t data; 389 #endif 390 if (once) 391 return reason; 392 393 once = 1; 394 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 395 return reason; 396 397 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 398 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 399 ERROR("BL2: REG Keep10 READ ERROR.\n"); 400 panic(); 401 } 402 403 if (KEEP10_MAGIC != data) 404 reason = RCAR_WARM_BOOT; 405 #else 406 reason = RCAR_WARM_BOOT; 407 #endif 408 return reason; 409 #else 410 return RCAR_COLD_BOOT; 411 #endif 412 } 413 414 #if RCAR_GEN3_BL33_GZIP == 1 415 void bl2_plat_preload_setup(void) 416 { 417 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip); 418 } 419 #endif 420 421 static uint64_t check_secure_load_area(uintptr_t base, uint32_t size, 422 uintptr_t dest, uint32_t len) 423 { 424 uintptr_t free_end, requested_end; 425 426 /* 427 * Handle corner cases first. 428 * 429 * The order of the 2 tests is important, because if there's no space 430 * left (i.e. free_size == 0) but we don't ask for any memory 431 * (i.e. size == 0) then we should report that the memory is free. 432 */ 433 if (len == 0U) { 434 WARN("BL2: load data size is zero\n"); 435 return 0; /* A zero-byte region is always free */ 436 } 437 if (size == 0U) { 438 goto err; 439 } 440 441 /* 442 * Check that the end addresses don't overflow. 443 * If they do, consider that this memory region is not free, as this 444 * is an invalid scenario. 445 */ 446 if (check_uptr_overflow(base, size - 1U)) { 447 goto err; 448 } 449 free_end = base + (size - 1U); 450 451 if (check_uptr_overflow(dest, len - 1U)) { 452 goto err; 453 } 454 requested_end = dest + (len - 1U); 455 456 /* 457 * Finally, check that the requested memory region lies within the free 458 * region. 459 */ 460 if ((dest < base) || (requested_end > free_end)) { 461 goto err; 462 } 463 464 return 0; 465 466 err: 467 ERROR("BL2: load data is outside the loadable area.\n"); 468 ERROR("BL2: dst=0x%lx, len=%d(0x%x)\n", dest, len, len); 469 return 1; 470 } 471 472 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest, 473 uint32_t *len) 474 { 475 uint32_t cert; 476 int ret; 477 478 ret = rcar_get_certificate(certid, &cert); 479 if (ret) { 480 ERROR("%s : cert file load error", __func__); 481 return 1; 482 } 483 484 rcar_read_certificate((uint64_t) cert, len, dest); 485 486 return 0; 487 } 488 489 int bl2_plat_handle_pre_image_load(unsigned int image_id) 490 { 491 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 492 bl_mem_params_node_t *bl_mem_params; 493 uintptr_t dev_handle; 494 uintptr_t image_spec; 495 uintptr_t dest; 496 uint32_t len; 497 uint64_t ui64_ret; 498 int iret; 499 500 bl_mem_params = get_bl_mem_params_node(image_id); 501 if (bl_mem_params == NULL) { 502 ERROR("BL2: Failed to get loading parameter.\n"); 503 return 1; 504 } 505 506 switch (image_id) { 507 case BL31_IMAGE_ID: 508 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) { 509 iret = plat_get_image_source(image_id, &dev_handle, 510 &image_spec); 511 if (iret != 0) { 512 return 1; 513 } 514 515 ui64_ret = rcar_get_dest_addr_from_cert( 516 SOC_FW_CONTENT_CERT_ID, &dest, &len); 517 if (ui64_ret != 0U) { 518 return 1; 519 } 520 521 ui64_ret = check_secure_load_area( 522 BL31_BASE, BL31_LIMIT - BL31_BASE, 523 dest, len); 524 if (ui64_ret != 0U) { 525 return 1; 526 } 527 528 *boot_kind = RCAR_COLD_BOOT; 529 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 530 531 bl_mem_params->image_info.image_base = dest; 532 bl_mem_params->image_info.image_size = len; 533 } else { 534 *boot_kind = RCAR_WARM_BOOT; 535 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 536 537 console_flush(); 538 bl2_plat_flush_bl31_params(); 539 540 /* will not return */ 541 bl2_enter_bl31(&bl_mem_params->ep_info); 542 } 543 544 return 0; 545 #ifndef SPD_NONE 546 case BL32_IMAGE_ID: 547 ui64_ret = rcar_get_dest_addr_from_cert( 548 TRUSTED_OS_FW_CONTENT_CERT_ID, &dest, &len); 549 if (ui64_ret != 0U) { 550 return 1; 551 } 552 553 ui64_ret = check_secure_load_area( 554 BL32_BASE, BL32_LIMIT - BL32_BASE, dest, len); 555 if (ui64_ret != 0U) { 556 return 1; 557 } 558 559 bl_mem_params->image_info.image_base = dest; 560 bl_mem_params->image_info.image_size = len; 561 562 return 0; 563 #endif 564 case BL33_IMAGE_ID: 565 /* case of image_id == BL33_IMAGE_ID */ 566 ui64_ret = rcar_get_dest_addr_from_cert( 567 NON_TRUSTED_FW_CONTENT_CERT_ID, 568 &dest, &len); 569 570 if (ui64_ret != 0U) { 571 return 1; 572 } 573 574 #if RCAR_GEN3_BL33_GZIP == 1 575 image_decompress_prepare(&bl_mem_params->image_info); 576 #endif 577 578 return 0; 579 default: 580 return 1; 581 } 582 583 return 0; 584 } 585 586 int bl2_plat_handle_post_image_load(unsigned int image_id) 587 { 588 static bl2_to_bl31_params_mem_t *params; 589 bl_mem_params_node_t *bl_mem_params; 590 591 if (!params) { 592 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 593 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 594 } 595 596 bl_mem_params = get_bl_mem_params_node(image_id); 597 if (!bl_mem_params) { 598 ERROR("BL2: Failed to get loading parameter.\n"); 599 return 1; 600 } 601 602 switch (image_id) { 603 case BL31_IMAGE_ID: 604 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 605 return 0; 606 case BL32_IMAGE_ID: 607 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 608 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 609 sizeof(entry_point_info_t)); 610 return 0; 611 case BL33_IMAGE_ID: 612 #if RCAR_GEN3_BL33_GZIP == 1 613 int ret; 614 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) { 615 /* decompress gzip-compressed image */ 616 ret = image_decompress(&bl_mem_params->image_info); 617 if (ret != 0) { 618 return ret; 619 } 620 } else { 621 /* plain image, copy it in place */ 622 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE, 623 bl_mem_params->image_info.image_size); 624 } 625 #endif 626 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 627 sizeof(entry_point_info_t)); 628 return 0; 629 default: 630 return 1; 631 } 632 633 return 0; 634 } 635 636 struct meminfo *bl2_plat_sec_mem_layout(void) 637 { 638 return &bl2_tzram_layout; 639 } 640 641 static void bl2_populate_compatible_string(void *dt) 642 { 643 uint32_t board_type; 644 uint32_t board_rev; 645 uint32_t reg; 646 int ret; 647 648 fdt_setprop_u32(dt, 0, "#address-cells", 2); 649 fdt_setprop_u32(dt, 0, "#size-cells", 2); 650 651 /* Populate compatible string */ 652 rcar_get_board_type(&board_type, &board_rev); 653 switch (board_type) { 654 case BOARD_SALVATOR_X: 655 ret = fdt_setprop_string(dt, 0, "compatible", 656 "renesas,salvator-x"); 657 break; 658 case BOARD_SALVATOR_XS: 659 ret = fdt_setprop_string(dt, 0, "compatible", 660 "renesas,salvator-xs"); 661 break; 662 case BOARD_STARTER_KIT: 663 ret = fdt_setprop_string(dt, 0, "compatible", 664 "renesas,m3ulcb"); 665 break; 666 case BOARD_STARTER_KIT_PRE: 667 ret = fdt_setprop_string(dt, 0, "compatible", 668 "renesas,h3ulcb"); 669 break; 670 case BOARD_EAGLE: 671 ret = fdt_setprop_string(dt, 0, "compatible", 672 "renesas,eagle"); 673 break; 674 case BOARD_EBISU: 675 case BOARD_EBISU_4D: 676 ret = fdt_setprop_string(dt, 0, "compatible", 677 "renesas,ebisu"); 678 break; 679 case BOARD_DRAAK: 680 ret = fdt_setprop_string(dt, 0, "compatible", 681 "renesas,draak"); 682 break; 683 default: 684 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 685 panic(); 686 } 687 688 if (ret < 0) { 689 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 690 panic(); 691 } 692 693 reg = mmio_read_32(RCAR_PRR); 694 switch (reg & PRR_PRODUCT_MASK) { 695 case PRR_PRODUCT_H3: 696 ret = fdt_appendprop_string(dt, 0, "compatible", 697 "renesas,r8a7795"); 698 break; 699 case PRR_PRODUCT_M3: 700 ret = fdt_appendprop_string(dt, 0, "compatible", 701 "renesas,r8a7796"); 702 break; 703 case PRR_PRODUCT_M3N: 704 ret = fdt_appendprop_string(dt, 0, "compatible", 705 "renesas,r8a77965"); 706 break; 707 case PRR_PRODUCT_V3M: 708 ret = fdt_appendprop_string(dt, 0, "compatible", 709 "renesas,r8a77970"); 710 break; 711 case PRR_PRODUCT_E3: 712 ret = fdt_appendprop_string(dt, 0, "compatible", 713 "renesas,r8a77990"); 714 break; 715 case PRR_PRODUCT_D3: 716 ret = fdt_appendprop_string(dt, 0, "compatible", 717 "renesas,r8a77995"); 718 break; 719 default: 720 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 721 panic(); 722 } 723 724 if (ret < 0) { 725 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 726 panic(); 727 } 728 } 729 730 static void bl2_add_rpc_node(void) 731 { 732 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0) 733 int ret, node; 734 735 node = ret = fdt_add_subnode(fdt, 0, "soc"); 736 if (ret < 0) { 737 goto err; 738 } 739 740 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000"); 741 if (ret < 0) { 742 goto err; 743 } 744 745 ret = fdt_setprop_string(fdt, node, "status", "okay"); 746 if (ret < 0) { 747 goto err; 748 } 749 750 return; 751 err: 752 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret); 753 panic(); 754 #endif 755 } 756 757 static void bl2_add_dram_entry(uint64_t start, uint64_t size) 758 { 759 char nodename[32] = { 0 }; 760 uint64_t fdtsize; 761 int ret, node; 762 763 fdtsize = cpu_to_fdt64(size); 764 765 snprintf(nodename, sizeof(nodename), "memory@"); 766 unsigned_num_print(start, 16, nodename + strlen(nodename)); 767 node = ret = fdt_add_subnode(fdt, 0, nodename); 768 if (ret < 0) { 769 goto err; 770 } 771 772 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 773 if (ret < 0) { 774 goto err; 775 } 776 777 ret = fdt_setprop_u64(fdt, node, "reg", start); 778 if (ret < 0) { 779 goto err; 780 } 781 782 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 783 sizeof(fdtsize)); 784 if (ret < 0) { 785 goto err; 786 } 787 788 return; 789 err: 790 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n", 791 start, start + size - 1, ret); 792 panic(); 793 } 794 795 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 796 { 797 uint64_t start, size, size32; 798 int chan; 799 800 for (chan = 0; chan < 4; chan++) { 801 start = dram_config[2 * chan]; 802 size = dram_config[2 * chan + 1]; 803 if (!size) 804 continue; 805 806 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n", 807 chan, start, start + size - 1, 808 (size >> 30) ? : size >> 20, 809 (size >> 30) ? "G" : "M"); 810 } 811 812 /* 813 * We add the DT nodes in reverse order here. The fdt_add_subnode() 814 * adds the DT node before the first existing DT node, so we have 815 * to add them in reverse order to get nodes sorted by address in 816 * the resulting DT. 817 */ 818 for (chan = 3; chan >= 0; chan--) { 819 start = dram_config[2 * chan]; 820 size = dram_config[2 * chan + 1]; 821 if (!size) 822 continue; 823 824 /* 825 * Channel 0 is mapped in 32bit space and the first 826 * 128 MiB are reserved and the maximum size is 2GiB. 827 */ 828 if (chan == 0) { 829 /* Limit the 32bit entry to 2 GiB - 128 MiB */ 830 size32 = size - 0x8000000U; 831 if (size32 >= 0x78000000U) { 832 size32 = 0x78000000U; 833 } 834 835 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */ 836 bl2_add_dram_entry(0x48000000, size32); 837 838 /* 839 * If channel 0 is less than 2 GiB long, the 840 * entire memory fits into the 32bit space entry, 841 * so move on to the next channel. 842 */ 843 if (size <= 0x80000000U) { 844 continue; 845 } 846 847 /* 848 * If channel 0 is more than 2 GiB long, emit 849 * another entry which covers the rest of the 850 * memory in channel 0, in the 64bit space. 851 * 852 * Start of this new entry is at 2 GiB offset 853 * from the beginning of the 64bit channel 0 854 * address, size is 2 GiB shorter than total 855 * size of the channel. 856 */ 857 start += 0x80000000U; 858 size -= 0x80000000U; 859 } 860 861 bl2_add_dram_entry(start, size); 862 } 863 } 864 865 static void bl2_advertise_dram_size(uint32_t product) 866 { 867 uint64_t dram_config[8] = { 868 [0] = 0x400000000ULL, 869 [2] = 0x500000000ULL, 870 [4] = 0x600000000ULL, 871 [6] = 0x700000000ULL, 872 }; 873 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; 874 875 switch (product) { 876 case PRR_PRODUCT_H3: 877 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 878 /* 4GB(1GBx4) */ 879 dram_config[1] = 0x40000000ULL; 880 dram_config[3] = 0x40000000ULL; 881 dram_config[5] = 0x40000000ULL; 882 dram_config[7] = 0x40000000ULL; 883 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 884 (RCAR_DRAM_CHANNEL == 5) && \ 885 (RCAR_DRAM_SPLIT == 2) 886 /* 4GB(2GBx2 2ch split) */ 887 dram_config[1] = 0x80000000ULL; 888 dram_config[3] = 0x80000000ULL; 889 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 890 /* 8GB(2GBx4: default) */ 891 dram_config[1] = 0x80000000ULL; 892 dram_config[3] = 0x80000000ULL; 893 dram_config[5] = 0x80000000ULL; 894 dram_config[7] = 0x80000000ULL; 895 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 896 break; 897 898 case PRR_PRODUCT_M3: 899 if (cut < PRR_PRODUCT_30) { 900 #if (RCAR_GEN3_ULCB == 1) 901 /* 2GB(1GBx2 2ch split) */ 902 dram_config[1] = 0x40000000ULL; 903 dram_config[5] = 0x40000000ULL; 904 #else 905 /* 4GB(2GBx2 2ch split) */ 906 dram_config[1] = 0x80000000ULL; 907 dram_config[5] = 0x80000000ULL; 908 #endif 909 } else { 910 /* 8GB(2GBx4 2ch split) */ 911 dram_config[1] = 0x100000000ULL; 912 dram_config[5] = 0x100000000ULL; 913 } 914 break; 915 916 case PRR_PRODUCT_M3N: 917 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2) 918 /* 4GB(4GBx1) */ 919 dram_config[1] = 0x100000000ULL; 920 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) 921 /* 2GB(1GBx2) */ 922 dram_config[1] = 0x80000000ULL; 923 #endif 924 break; 925 926 case PRR_PRODUCT_V3M: 927 /* 1GB(512MBx2) */ 928 dram_config[1] = 0x40000000ULL; 929 break; 930 931 case PRR_PRODUCT_E3: 932 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 933 /* 1GB(512MBx2) */ 934 dram_config[1] = 0x40000000ULL; 935 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 936 /* 2GB(512MBx4) */ 937 dram_config[1] = 0x80000000ULL; 938 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 939 /* 4GB(1GBx4) */ 940 dram_config[1] = 0x100000000ULL; 941 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 942 break; 943 944 case PRR_PRODUCT_D3: 945 /* 512MB */ 946 dram_config[1] = 0x20000000ULL; 947 break; 948 } 949 950 bl2_advertise_dram_entries(dram_config); 951 } 952 953 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 954 u_register_t arg3, u_register_t arg4) 955 { 956 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 957 uint32_t product, product_cut, major, minor; 958 int32_t ret; 959 const char *str; 960 const char *unknown = "unknown"; 961 const char *cpu_ca57 = "CA57"; 962 const char *cpu_ca53 = "CA53"; 963 const char *product_m3n = "M3N"; 964 const char *product_h3 = "H3"; 965 const char *product_m3 = "M3"; 966 const char *product_e3 = "E3"; 967 const char *product_d3 = "D3"; 968 const char *product_v3m = "V3M"; 969 const char *lcs_secure = "SE"; 970 const char *lcs_cm = "CM"; 971 const char *lcs_dm = "DM"; 972 const char *lcs_sd = "SD"; 973 const char *lcs_fa = "FA"; 974 const char *sscg_off = "PLL1 nonSSCG Clock select"; 975 const char *sscg_on = "PLL1 SSCG Clock select"; 976 const char *boot_hyper80 = "HyperFlash(80MHz)"; 977 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 978 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 979 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 980 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 981 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 982 const char *boot_hyper160 = "HyperFlash(150MHz)"; 983 #else 984 const char *boot_hyper160 = "HyperFlash(160MHz)"; 985 #endif 986 987 bl2_init_generic_timer(); 988 989 reg = mmio_read_32(RCAR_MODEMR); 990 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 991 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 992 993 bl2_cpg_init(); 994 995 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 996 boot_cpu == MODEMR_BOOT_CPU_CA53) { 997 rcar_pfc_init(); 998 rcar_console_boot_init(); 999 } 1000 1001 plat_rcar_gic_driver_init(); 1002 plat_rcar_gic_init(); 1003 rcar_swdt_init(); 1004 1005 /* FIQ interrupts are taken to EL3 */ 1006 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 1007 1008 write_daifclr(DAIF_FIQ_BIT); 1009 1010 reg = read_midr(); 1011 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 1012 switch (midr) { 1013 case MIDR_CA57: 1014 str = cpu_ca57; 1015 break; 1016 case MIDR_CA53: 1017 str = cpu_ca53; 1018 break; 1019 default: 1020 str = unknown; 1021 break; 1022 } 1023 1024 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 1025 version_of_renesas); 1026 1027 reg = mmio_read_32(RCAR_PRR); 1028 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1029 product = reg & PRR_PRODUCT_MASK; 1030 1031 switch (product) { 1032 case PRR_PRODUCT_H3: 1033 str = product_h3; 1034 break; 1035 case PRR_PRODUCT_M3: 1036 str = product_m3; 1037 break; 1038 case PRR_PRODUCT_M3N: 1039 str = product_m3n; 1040 break; 1041 case PRR_PRODUCT_V3M: 1042 str = product_v3m; 1043 break; 1044 case PRR_PRODUCT_E3: 1045 str = product_e3; 1046 break; 1047 case PRR_PRODUCT_D3: 1048 str = product_d3; 1049 break; 1050 default: 1051 str = unknown; 1052 break; 1053 } 1054 1055 if ((PRR_PRODUCT_M3 == product) && 1056 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 1057 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 1058 /* M3 Ver.1.1 or Ver.1.2 */ 1059 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 1060 str); 1061 } else { 1062 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 1063 str, 1064 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 1065 } 1066 } else if (product == PRR_PRODUCT_D3) { 1067 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) { 1068 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str); 1069 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 1070 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str); 1071 } else { 1072 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str); 1073 } 1074 } else { 1075 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 1076 major = major + RCAR_MAJOR_OFFSET; 1077 minor = reg & RCAR_MINOR_MASK; 1078 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 1079 } 1080 1081 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) { 1082 reg = mmio_read_32(RCAR_MODEMR); 1083 sscg = reg & RCAR_SSCG_MASK; 1084 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 1085 NOTICE("BL2: %s\n", str); 1086 } 1087 1088 rcar_get_board_type(&type, &rev); 1089 1090 switch (type) { 1091 case BOARD_SALVATOR_X: 1092 case BOARD_KRIEK: 1093 case BOARD_STARTER_KIT: 1094 case BOARD_SALVATOR_XS: 1095 case BOARD_EBISU: 1096 case BOARD_STARTER_KIT_PRE: 1097 case BOARD_EBISU_4D: 1098 case BOARD_DRAAK: 1099 case BOARD_EAGLE: 1100 break; 1101 default: 1102 type = BOARD_UNKNOWN; 1103 break; 1104 } 1105 1106 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 1107 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 1108 else { 1109 NOTICE("BL2: Board is %s Rev.%d.%d\n", 1110 GET_BOARD_NAME(type), 1111 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 1112 } 1113 1114 #if RCAR_LSI != RCAR_AUTO 1115 if (product != TARGET_PRODUCT) { 1116 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 1117 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 1118 panic(); 1119 } 1120 #endif 1121 rcar_avs_init(); 1122 rcar_avs_setting(); 1123 1124 switch (boot_dev) { 1125 case MODEMR_BOOT_DEV_HYPERFLASH160: 1126 str = boot_hyper160; 1127 break; 1128 case MODEMR_BOOT_DEV_HYPERFLASH80: 1129 str = boot_hyper80; 1130 break; 1131 case MODEMR_BOOT_DEV_QSPI_FLASH40: 1132 str = boot_qspi40; 1133 break; 1134 case MODEMR_BOOT_DEV_QSPI_FLASH80: 1135 str = boot_qspi80; 1136 break; 1137 case MODEMR_BOOT_DEV_EMMC_25X1: 1138 #if RCAR_LSI == RCAR_D3 1139 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 1140 panic(); 1141 #endif 1142 str = boot_emmc25x1; 1143 break; 1144 case MODEMR_BOOT_DEV_EMMC_50X8: 1145 str = boot_emmc50x8; 1146 break; 1147 default: 1148 str = unknown; 1149 break; 1150 } 1151 NOTICE("BL2: Boot device is %s\n", str); 1152 1153 rcar_avs_setting(); 1154 reg = rcar_rom_get_lcs(&lcs); 1155 if (reg) { 1156 str = unknown; 1157 goto lcm_state; 1158 } 1159 1160 switch (lcs) { 1161 case LCS_CM: 1162 str = lcs_cm; 1163 break; 1164 case LCS_DM: 1165 str = lcs_dm; 1166 break; 1167 case LCS_SD: 1168 str = lcs_sd; 1169 break; 1170 case LCS_SE: 1171 str = lcs_secure; 1172 break; 1173 case LCS_FA: 1174 str = lcs_fa; 1175 break; 1176 default: 1177 str = unknown; 1178 break; 1179 } 1180 1181 lcm_state: 1182 NOTICE("BL2: LCM state is %s\n", str); 1183 1184 rcar_avs_end(); 1185 is_ddr_backup_mode(); 1186 1187 bl2_tzram_layout.total_base = BL31_BASE; 1188 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 1189 1190 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 1191 boot_cpu == MODEMR_BOOT_CPU_CA53) { 1192 ret = rcar_dram_init(); 1193 if (ret) { 1194 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 1195 panic(); 1196 } 1197 rcar_qos_init(); 1198 } 1199 1200 /* Set up FDT */ 1201 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 1202 if (ret) { 1203 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 1204 panic(); 1205 } 1206 1207 /* Add platform compatible string */ 1208 bl2_populate_compatible_string(fdt); 1209 1210 /* Enable RPC if unlocked */ 1211 bl2_add_rpc_node(); 1212 1213 /* Print DRAM layout */ 1214 bl2_advertise_dram_size(product); 1215 1216 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1217 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 1218 if (rcar_emmc_init() != EMMC_SUCCESS) { 1219 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 1220 panic(); 1221 } 1222 rcar_emmc_memcard_power(EMMC_POWER_ON); 1223 if (rcar_emmc_mount() != EMMC_SUCCESS) { 1224 NOTICE("BL2: Failed to eMMC mount operation.\n"); 1225 panic(); 1226 } 1227 } else { 1228 rcar_rpc_init(); 1229 rcar_dma_init(); 1230 } 1231 1232 reg = mmio_read_32(RST_WDTRSTCR); 1233 reg &= ~WDTRSTCR_RWDT_RSTMSK; 1234 reg |= WDTRSTCR_PASSWORD; 1235 mmio_write_32(RST_WDTRSTCR, reg); 1236 1237 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 1238 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 1239 1240 reg = mmio_read_32(RCAR_PRR); 1241 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 1242 mmio_write_32(CPG_CA57DBGRCR, 1243 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 1244 1245 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 1246 mmio_write_32(CPG_CA53DBGRCR, 1247 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 1248 1249 if (product_cut == PRR_PRODUCT_H3_CUT10) { 1250 reg = mmio_read_32(CPG_PLL2CR); 1251 reg &= ~((uint32_t) 1 << 5); 1252 mmio_write_32(CPG_PLL2CR, reg); 1253 1254 reg = mmio_read_32(CPG_PLL4CR); 1255 reg &= ~((uint32_t) 1 << 5); 1256 mmio_write_32(CPG_PLL4CR, reg); 1257 1258 reg = mmio_read_32(CPG_PLL0CR); 1259 reg &= ~((uint32_t) 1 << 12); 1260 mmio_write_32(CPG_PLL0CR, reg); 1261 } 1262 1263 bl2_create_fcnl_reserved_memory(); 1264 1265 fdt_pack(fdt); 1266 NOTICE("BL2: FDT at %p\n", fdt); 1267 1268 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1269 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1270 rcar_io_emmc_setup(); 1271 else 1272 rcar_io_setup(); 1273 } 1274 1275 void bl2_el3_plat_arch_setup(void) 1276 { 1277 #if RCAR_BL2_DCACHE == 1 1278 NOTICE("BL2: D-Cache enable\n"); 1279 rcar_configure_mmu_el3(BL2_BASE, 1280 BL2_END - BL2_BASE, 1281 BL2_RO_BASE, BL2_RO_LIMIT 1282 #if USE_COHERENT_MEM 1283 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1284 #endif 1285 ); 1286 #endif 1287 } 1288 1289 void bl2_el3_plat_prepare_exit(void) 1290 { 1291 bl2_ram_security_setting_finish(); 1292 } 1293 1294 void bl2_platform_setup(void) 1295 { 1296 1297 } 1298 1299 static void bl2_init_generic_timer(void) 1300 { 1301 /* FIXME: V3M 16.666 MHz ? */ 1302 #if RCAR_LSI == RCAR_D3 1303 uint32_t reg_cntfid = EXTAL_DRAAK; 1304 #elif RCAR_LSI == RCAR_E3 1305 uint32_t reg_cntfid = EXTAL_EBISU; 1306 #else /* RCAR_LSI == RCAR_E3 */ 1307 uint32_t reg; 1308 uint32_t reg_cntfid; 1309 uint32_t modemr; 1310 uint32_t modemr_pll; 1311 uint32_t board_type; 1312 uint32_t board_rev; 1313 uint32_t pll_table[] = { 1314 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1315 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1316 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1317 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1318 }; 1319 1320 modemr = mmio_read_32(RCAR_MODEMR); 1321 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1322 1323 /* Set frequency data in CNTFID0 */ 1324 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1325 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1326 switch (modemr_pll) { 1327 case MD14_MD13_TYPE_0: 1328 rcar_get_board_type(&board_type, &board_rev); 1329 if (BOARD_SALVATOR_XS == board_type) { 1330 reg_cntfid = EXTAL_SALVATOR_XS; 1331 } 1332 break; 1333 case MD14_MD13_TYPE_3: 1334 if (PRR_PRODUCT_H3_CUT10 == reg) { 1335 reg_cntfid = reg_cntfid >> 1U; 1336 } 1337 break; 1338 default: 1339 /* none */ 1340 break; 1341 } 1342 #endif /* RCAR_LSI == RCAR_E3 */ 1343 /* Update memory mapped and register based frequency */ 1344 write_cntfrq_el0((u_register_t )reg_cntfid); 1345 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1346 /* Enable counter */ 1347 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1348 (uint32_t)CNTCR_EN); 1349 } 1350