1 /* 2 * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/desc_image_load.h> 18 #include <common/image_decompress.h> 19 #include <drivers/console.h> 20 #include <drivers/io/io_driver.h> 21 #include <drivers/io/io_storage.h> 22 #include <lib/mmio.h> 23 #include <lib/xlat_tables/xlat_tables_defs.h> 24 #include <plat/common/platform.h> 25 #if RCAR_GEN3_BL33_GZIP == 1 26 #include <tf_gunzip.h> 27 #endif 28 29 #include "avs_driver.h" 30 #include "boot_init_dram.h" 31 #include "cpg_registers.h" 32 #include "board.h" 33 #include "emmc_def.h" 34 #include "emmc_hal.h" 35 #include "emmc_std.h" 36 37 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 38 #include "iic_dvfs.h" 39 #endif 40 41 #include "io_common.h" 42 #include "io_rcar.h" 43 #include "qos_init.h" 44 #include "rcar_def.h" 45 #include "rcar_private.h" 46 #include "rcar_version.h" 47 #include "rom_api.h" 48 49 #if RCAR_BL2_DCACHE == 1 50 /* 51 * Following symbols are only used during plat_arch_setup() only 52 * when RCAR_BL2_DCACHE is enabled. 53 */ 54 static const uint64_t BL2_RO_BASE = BL_CODE_BASE; 55 static const uint64_t BL2_RO_LIMIT = BL_CODE_END; 56 57 #if USE_COHERENT_MEM 58 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 59 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 60 #endif 61 62 #endif 63 64 extern void plat_rcar_gic_driver_init(void); 65 extern void plat_rcar_gic_init(void); 66 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info); 67 extern void bl2_system_cpg_init(void); 68 extern void bl2_secure_setting(void); 69 extern void bl2_cpg_init(void); 70 extern void rcar_io_emmc_setup(void); 71 extern void rcar_io_setup(void); 72 extern void rcar_swdt_release(void); 73 extern void rcar_swdt_init(void); 74 extern void rcar_rpc_init(void); 75 extern void rcar_pfc_init(void); 76 extern void rcar_dma_init(void); 77 78 static void bl2_init_generic_timer(void); 79 80 /* R-Car Gen3 product check */ 81 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) 82 #define TARGET_PRODUCT PRR_PRODUCT_H3 83 #define TARGET_NAME "R-Car H3" 84 #elif RCAR_LSI == RCAR_M3 85 #define TARGET_PRODUCT PRR_PRODUCT_M3 86 #define TARGET_NAME "R-Car M3" 87 #elif RCAR_LSI == RCAR_M3N 88 #define TARGET_PRODUCT PRR_PRODUCT_M3N 89 #define TARGET_NAME "R-Car M3N" 90 #elif RCAR_LSI == RCAR_V3M 91 #define TARGET_PRODUCT PRR_PRODUCT_V3M 92 #define TARGET_NAME "R-Car V3M" 93 #elif RCAR_LSI == RCAR_E3 94 #define TARGET_PRODUCT PRR_PRODUCT_E3 95 #define TARGET_NAME "R-Car E3" 96 #elif RCAR_LSI == RCAR_D3 97 #define TARGET_PRODUCT PRR_PRODUCT_D3 98 #define TARGET_NAME "R-Car D3" 99 #elif RCAR_LSI == RCAR_AUTO 100 #define TARGET_NAME "R-Car H3/M3/M3N/V3M" 101 #endif 102 103 #if (RCAR_LSI == RCAR_E3) 104 #define GPIO_INDT (GPIO_INDT6) 105 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U) 106 #else 107 #define GPIO_INDT (GPIO_INDT1) 108 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U) 109 #endif 110 111 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100) 112 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), 113 assert_bl31_params_do_not_fit_in_shared_memory); 114 115 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 116 117 /* FDT with DRAM configuration */ 118 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)]; 119 static void *fdt = (void *)fdt_blob; 120 121 static void unsigned_num_print(unsigned long long int unum, unsigned int radix, 122 char *string) 123 { 124 /* Just need enough space to store 64 bit decimal integer */ 125 char num_buf[20]; 126 int i = 0; 127 unsigned int rem; 128 129 do { 130 rem = unum % radix; 131 if (rem < 0xa) 132 num_buf[i] = '0' + rem; 133 else 134 num_buf[i] = 'a' + (rem - 0xa); 135 i++; 136 unum /= radix; 137 } while (unum > 0U); 138 139 while (--i >= 0) 140 *string++ = num_buf[i]; 141 *string = 0; 142 } 143 144 #if (RCAR_LOSSY_ENABLE == 1) 145 typedef struct bl2_lossy_info { 146 uint32_t magic; 147 uint32_t a0; 148 uint32_t b0; 149 } bl2_lossy_info_t; 150 151 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr, 152 uint64_t end_addr, uint32_t format, 153 uint32_t enable, int fcnlnode) 154 { 155 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr); 156 char nodename[40] = { 0 }; 157 int ret, node; 158 159 /* Ignore undefined addresses */ 160 if (start_addr == 0 && end_addr == 0) 161 return; 162 163 snprintf(nodename, sizeof(nodename), "lossy-decompression@"); 164 unsigned_num_print(start_addr, 16, nodename + strlen(nodename)); 165 166 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename); 167 if (ret < 0) { 168 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret); 169 panic(); 170 } 171 172 ret = fdt_setprop_string(fdt, node, "compatible", 173 "renesas,lossy-decompression"); 174 if (ret < 0) { 175 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret); 176 panic(); 177 } 178 179 ret = fdt_appendprop_string(fdt, node, "compatible", 180 "shared-dma-pool"); 181 if (ret < 0) { 182 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret); 183 panic(); 184 } 185 186 ret = fdt_setprop_u64(fdt, node, "reg", start_addr); 187 if (ret < 0) { 188 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret); 189 panic(); 190 } 191 192 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize)); 193 if (ret < 0) { 194 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret); 195 panic(); 196 } 197 198 ret = fdt_setprop(fdt, node, "no-map", NULL, 0); 199 if (ret < 0) { 200 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret); 201 panic(); 202 } 203 204 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format); 205 if (ret < 0) { 206 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret); 207 panic(); 208 } 209 } 210 211 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, 212 uint64_t end_addr, uint32_t format, 213 uint32_t enable, int fcnlnode) 214 { 215 bl2_lossy_info_t info; 216 uint32_t reg; 217 218 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode); 219 220 reg = format | (start_addr >> 20); 221 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); 222 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20); 223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); 224 225 info.magic = 0x12345678U; 226 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); 227 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); 228 229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic); 230 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0); 231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0); 232 233 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, 234 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), 235 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); 236 } 237 #endif 238 239 void bl2_plat_flush_bl31_params(void) 240 { 241 uint32_t product_cut, product, cut; 242 uint32_t boot_dev, boot_cpu; 243 uint32_t lcs, reg, val; 244 245 reg = mmio_read_32(RCAR_MODEMR); 246 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 247 248 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 249 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 250 emmc_terminate(); 251 252 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) 253 bl2_secure_setting(); 254 255 reg = mmio_read_32(RCAR_PRR); 256 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 257 product = reg & PRR_PRODUCT_MASK; 258 cut = reg & PRR_CUT_MASK; 259 260 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut) 261 goto tlb; 262 263 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut) 264 goto tlb; 265 266 /* Disable MFIS write protection */ 267 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1); 268 269 tlb: 270 reg = mmio_read_32(RCAR_MODEMR); 271 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 272 if (boot_cpu != MODEMR_BOOT_CPU_CA57 && 273 boot_cpu != MODEMR_BOOT_CPU_CA53) 274 goto mmu; 275 276 if (product_cut == PRR_PRODUCT_H3_CUT20) { 277 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 278 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); 279 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 280 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); 281 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); 282 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); 283 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 284 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) { 285 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 286 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 287 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) || 288 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) { 289 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); 290 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); 291 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); 292 } 293 294 if (product_cut == (PRR_PRODUCT_H3_CUT20) || 295 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) || 296 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) || 297 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) { 298 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); 299 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); 300 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); 301 302 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE); 303 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE); 304 } 305 306 mmu: 307 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE); 308 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT); 309 310 val = rcar_rom_get_lcs(&lcs); 311 if (val) { 312 ERROR("BL2: Failed to get the LCS. (%d)\n", val); 313 panic(); 314 } 315 316 if (lcs == LCS_SE) 317 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT); 318 319 rcar_swdt_release(); 320 bl2_system_cpg_init(); 321 322 #if RCAR_BL2_DCACHE == 1 323 /* Disable data cache (clean and invalidate) */ 324 disable_mmu_el3(); 325 #endif 326 } 327 328 static uint32_t is_ddr_backup_mode(void) 329 { 330 #if RCAR_SYSTEM_SUSPEND 331 static uint32_t reason = RCAR_COLD_BOOT; 332 static uint32_t once; 333 334 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 335 uint8_t data; 336 #endif 337 if (once) 338 return reason; 339 340 once = 1; 341 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0) 342 return reason; 343 344 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR 345 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) { 346 ERROR("BL2: REG Keep10 READ ERROR.\n"); 347 panic(); 348 } 349 350 if (KEEP10_MAGIC != data) 351 reason = RCAR_WARM_BOOT; 352 #else 353 reason = RCAR_WARM_BOOT; 354 #endif 355 return reason; 356 #else 357 return RCAR_COLD_BOOT; 358 #endif 359 } 360 361 #if RCAR_GEN3_BL33_GZIP == 1 362 void bl2_plat_preload_setup(void) 363 { 364 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip); 365 } 366 #endif 367 368 int bl2_plat_handle_pre_image_load(unsigned int image_id) 369 { 370 u_register_t *boot_kind = (void *) BOOT_KIND_BASE; 371 bl_mem_params_node_t *bl_mem_params; 372 373 bl_mem_params = get_bl_mem_params_node(image_id); 374 375 #if RCAR_GEN3_BL33_GZIP == 1 376 if (image_id == BL33_IMAGE_ID) { 377 image_decompress_prepare(&bl_mem_params->image_info); 378 } 379 #endif 380 381 if (image_id != BL31_IMAGE_ID) 382 return 0; 383 384 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) 385 goto cold_boot; 386 387 *boot_kind = RCAR_WARM_BOOT; 388 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 389 390 console_flush(); 391 bl2_plat_flush_bl31_params(); 392 393 /* will not return */ 394 bl2_enter_bl31(&bl_mem_params->ep_info); 395 396 cold_boot: 397 *boot_kind = RCAR_COLD_BOOT; 398 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind)); 399 400 return 0; 401 } 402 403 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest) 404 { 405 uint32_t cert, len; 406 int ret; 407 408 ret = rcar_get_certificate(certid, &cert); 409 if (ret) { 410 ERROR("%s : cert file load error", __func__); 411 return 1; 412 } 413 414 rcar_read_certificate((uint64_t) cert, &len, dest); 415 416 return 0; 417 } 418 419 int bl2_plat_handle_post_image_load(unsigned int image_id) 420 { 421 static bl2_to_bl31_params_mem_t *params; 422 bl_mem_params_node_t *bl_mem_params; 423 uintptr_t dest; 424 int ret; 425 426 if (!params) { 427 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE; 428 memset((void *)PARAMS_BASE, 0, sizeof(*params)); 429 } 430 431 bl_mem_params = get_bl_mem_params_node(image_id); 432 433 switch (image_id) { 434 case BL31_IMAGE_ID: 435 ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID, 436 &dest); 437 if (!ret) 438 bl_mem_params->image_info.image_base = dest; 439 break; 440 case BL32_IMAGE_ID: 441 ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID, 442 &dest); 443 if (!ret) 444 bl_mem_params->image_info.image_base = dest; 445 446 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, 447 sizeof(entry_point_info_t)); 448 break; 449 case BL33_IMAGE_ID: 450 #if RCAR_GEN3_BL33_GZIP == 1 451 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) { 452 /* decompress gzip-compressed image */ 453 ret = image_decompress(&bl_mem_params->image_info); 454 if (ret != 0) { 455 return ret; 456 } 457 } else { 458 /* plain image, copy it in place */ 459 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE, 460 bl_mem_params->image_info.image_size); 461 } 462 #endif 463 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, 464 sizeof(entry_point_info_t)); 465 break; 466 } 467 468 return 0; 469 } 470 471 struct meminfo *bl2_plat_sec_mem_layout(void) 472 { 473 return &bl2_tzram_layout; 474 } 475 476 static void bl2_populate_compatible_string(void *dt) 477 { 478 uint32_t board_type; 479 uint32_t board_rev; 480 uint32_t reg; 481 int ret; 482 483 fdt_setprop_u32(dt, 0, "#address-cells", 2); 484 fdt_setprop_u32(dt, 0, "#size-cells", 2); 485 486 /* Populate compatible string */ 487 rcar_get_board_type(&board_type, &board_rev); 488 switch (board_type) { 489 case BOARD_SALVATOR_X: 490 ret = fdt_setprop_string(dt, 0, "compatible", 491 "renesas,salvator-x"); 492 break; 493 case BOARD_SALVATOR_XS: 494 ret = fdt_setprop_string(dt, 0, "compatible", 495 "renesas,salvator-xs"); 496 break; 497 case BOARD_STARTER_KIT: 498 ret = fdt_setprop_string(dt, 0, "compatible", 499 "renesas,m3ulcb"); 500 break; 501 case BOARD_STARTER_KIT_PRE: 502 ret = fdt_setprop_string(dt, 0, "compatible", 503 "renesas,h3ulcb"); 504 break; 505 case BOARD_EAGLE: 506 ret = fdt_setprop_string(dt, 0, "compatible", 507 "renesas,eagle"); 508 break; 509 case BOARD_EBISU: 510 case BOARD_EBISU_4D: 511 ret = fdt_setprop_string(dt, 0, "compatible", 512 "renesas,ebisu"); 513 break; 514 case BOARD_DRAAK: 515 ret = fdt_setprop_string(dt, 0, "compatible", 516 "renesas,draak"); 517 break; 518 default: 519 NOTICE("BL2: Cannot set compatible string, board unsupported\n"); 520 panic(); 521 } 522 523 if (ret < 0) { 524 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 525 panic(); 526 } 527 528 reg = mmio_read_32(RCAR_PRR); 529 switch (reg & PRR_PRODUCT_MASK) { 530 case PRR_PRODUCT_H3: 531 ret = fdt_appendprop_string(dt, 0, "compatible", 532 "renesas,r8a7795"); 533 break; 534 case PRR_PRODUCT_M3: 535 ret = fdt_appendprop_string(dt, 0, "compatible", 536 "renesas,r8a7796"); 537 break; 538 case PRR_PRODUCT_M3N: 539 ret = fdt_appendprop_string(dt, 0, "compatible", 540 "renesas,r8a77965"); 541 break; 542 case PRR_PRODUCT_V3M: 543 ret = fdt_appendprop_string(dt, 0, "compatible", 544 "renesas,r8a77970"); 545 break; 546 case PRR_PRODUCT_E3: 547 ret = fdt_appendprop_string(dt, 0, "compatible", 548 "renesas,r8a77990"); 549 break; 550 case PRR_PRODUCT_D3: 551 ret = fdt_appendprop_string(dt, 0, "compatible", 552 "renesas,r8a77995"); 553 break; 554 default: 555 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n"); 556 panic(); 557 } 558 559 if (ret < 0) { 560 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret); 561 panic(); 562 } 563 } 564 565 static void bl2_add_rpc_node(void) 566 { 567 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0) 568 int ret, node; 569 570 node = ret = fdt_add_subnode(fdt, 0, "soc"); 571 if (ret < 0) { 572 goto err; 573 } 574 575 node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000"); 576 if (ret < 0) { 577 goto err; 578 } 579 580 ret = fdt_setprop_string(fdt, node, "status", "okay"); 581 if (ret < 0) { 582 goto err; 583 } 584 585 return; 586 err: 587 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret); 588 panic(); 589 #endif 590 } 591 592 static void bl2_add_dram_entry(uint64_t start, uint64_t size) 593 { 594 char nodename[32] = { 0 }; 595 uint64_t fdtsize; 596 int ret, node; 597 598 fdtsize = cpu_to_fdt64(size); 599 600 snprintf(nodename, sizeof(nodename), "memory@"); 601 unsigned_num_print(start, 16, nodename + strlen(nodename)); 602 node = ret = fdt_add_subnode(fdt, 0, nodename); 603 if (ret < 0) { 604 goto err; 605 } 606 607 ret = fdt_setprop_string(fdt, node, "device_type", "memory"); 608 if (ret < 0) { 609 goto err; 610 } 611 612 ret = fdt_setprop_u64(fdt, node, "reg", start); 613 if (ret < 0) { 614 goto err; 615 } 616 617 ret = fdt_appendprop(fdt, node, "reg", &fdtsize, 618 sizeof(fdtsize)); 619 if (ret < 0) { 620 goto err; 621 } 622 623 return; 624 err: 625 NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n", 626 start, start + size - 1, ret); 627 panic(); 628 } 629 630 static void bl2_advertise_dram_entries(uint64_t dram_config[8]) 631 { 632 uint64_t start, size, size32; 633 int chan; 634 635 for (chan = 0; chan < 4; chan++) { 636 start = dram_config[2 * chan]; 637 size = dram_config[2 * chan + 1]; 638 if (!size) 639 continue; 640 641 NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n", 642 chan, start, start + size - 1, 643 (size >> 30) ? : size >> 20, 644 (size >> 30) ? "G" : "M"); 645 } 646 647 /* 648 * We add the DT nodes in reverse order here. The fdt_add_subnode() 649 * adds the DT node before the first existing DT node, so we have 650 * to add them in reverse order to get nodes sorted by address in 651 * the resulting DT. 652 */ 653 for (chan = 3; chan >= 0; chan--) { 654 start = dram_config[2 * chan]; 655 size = dram_config[2 * chan + 1]; 656 if (!size) 657 continue; 658 659 /* 660 * Channel 0 is mapped in 32bit space and the first 661 * 128 MiB are reserved and the maximum size is 2GiB. 662 */ 663 if (chan == 0) { 664 /* Limit the 32bit entry to 2 GiB - 128 MiB */ 665 size32 = size - 0x8000000U; 666 if (size32 >= 0x78000000U) { 667 size32 = 0x78000000U; 668 } 669 670 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */ 671 bl2_add_dram_entry(0x48000000, size32); 672 673 /* 674 * If channel 0 is less than 2 GiB long, the 675 * entire memory fits into the 32bit space entry, 676 * so move on to the next channel. 677 */ 678 if (size <= 0x80000000U) { 679 continue; 680 } 681 682 /* 683 * If channel 0 is more than 2 GiB long, emit 684 * another entry which covers the rest of the 685 * memory in channel 0, in the 64bit space. 686 * 687 * Start of this new entry is at 2 GiB offset 688 * from the beginning of the 64bit channel 0 689 * address, size is 2 GiB shorter than total 690 * size of the channel. 691 */ 692 start += 0x80000000U; 693 size -= 0x80000000U; 694 } 695 696 bl2_add_dram_entry(start, size); 697 } 698 } 699 700 static void bl2_advertise_dram_size(uint32_t product) 701 { 702 uint64_t dram_config[8] = { 703 [0] = 0x400000000ULL, 704 [2] = 0x500000000ULL, 705 [4] = 0x600000000ULL, 706 [6] = 0x700000000ULL, 707 }; 708 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK; 709 710 switch (product) { 711 case PRR_PRODUCT_H3: 712 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) 713 /* 4GB(1GBx4) */ 714 dram_config[1] = 0x40000000ULL; 715 dram_config[3] = 0x40000000ULL; 716 dram_config[5] = 0x40000000ULL; 717 dram_config[7] = 0x40000000ULL; 718 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ 719 (RCAR_DRAM_CHANNEL == 5) && \ 720 (RCAR_DRAM_SPLIT == 2) 721 /* 4GB(2GBx2 2ch split) */ 722 dram_config[1] = 0x80000000ULL; 723 dram_config[3] = 0x80000000ULL; 724 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) 725 /* 8GB(2GBx4: default) */ 726 dram_config[1] = 0x80000000ULL; 727 dram_config[3] = 0x80000000ULL; 728 dram_config[5] = 0x80000000ULL; 729 dram_config[7] = 0x80000000ULL; 730 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ 731 break; 732 733 case PRR_PRODUCT_M3: 734 if (cut < PRR_PRODUCT_30) { 735 #if (RCAR_GEN3_ULCB == 1) 736 /* 2GB(1GBx2 2ch split) */ 737 dram_config[1] = 0x40000000ULL; 738 dram_config[5] = 0x40000000ULL; 739 #else 740 /* 4GB(2GBx2 2ch split) */ 741 dram_config[1] = 0x80000000ULL; 742 dram_config[5] = 0x80000000ULL; 743 #endif 744 } else { 745 /* 8GB(2GBx4 2ch split) */ 746 dram_config[1] = 0x100000000ULL; 747 dram_config[5] = 0x100000000ULL; 748 } 749 break; 750 751 case PRR_PRODUCT_M3N: 752 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2) 753 /* 4GB(4GBx1) */ 754 dram_config[1] = 0x100000000ULL; 755 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) 756 /* 2GB(1GBx2) */ 757 dram_config[1] = 0x80000000ULL; 758 #endif 759 break; 760 761 case PRR_PRODUCT_V3M: 762 /* 1GB(512MBx2) */ 763 dram_config[1] = 0x40000000ULL; 764 break; 765 766 case PRR_PRODUCT_E3: 767 #if (RCAR_DRAM_DDR3L_MEMCONF == 0) 768 /* 1GB(512MBx2) */ 769 dram_config[1] = 0x40000000ULL; 770 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) 771 /* 2GB(512MBx4) */ 772 dram_config[1] = 0x80000000ULL; 773 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) 774 /* 4GB(1GBx4) */ 775 dram_config[1] = 0x100000000ULL; 776 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ 777 break; 778 779 case PRR_PRODUCT_D3: 780 /* 512MB */ 781 dram_config[1] = 0x20000000ULL; 782 break; 783 } 784 785 bl2_advertise_dram_entries(dram_config); 786 } 787 788 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 789 u_register_t arg3, u_register_t arg4) 790 { 791 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev; 792 uint32_t product, product_cut, major, minor; 793 int32_t ret; 794 const char *str; 795 const char *unknown = "unknown"; 796 const char *cpu_ca57 = "CA57"; 797 const char *cpu_ca53 = "CA53"; 798 const char *product_m3n = "M3N"; 799 const char *product_h3 = "H3"; 800 const char *product_m3 = "M3"; 801 const char *product_e3 = "E3"; 802 const char *product_d3 = "D3"; 803 const char *product_v3m = "V3M"; 804 const char *lcs_secure = "SE"; 805 const char *lcs_cm = "CM"; 806 const char *lcs_dm = "DM"; 807 const char *lcs_sd = "SD"; 808 const char *lcs_fa = "FA"; 809 const char *sscg_off = "PLL1 nonSSCG Clock select"; 810 const char *sscg_on = "PLL1 SSCG Clock select"; 811 const char *boot_hyper80 = "HyperFlash(80MHz)"; 812 const char *boot_qspi40 = "QSPI Flash(40MHz)"; 813 const char *boot_qspi80 = "QSPI Flash(80MHz)"; 814 const char *boot_emmc25x1 = "eMMC(25MHz x1)"; 815 const char *boot_emmc50x8 = "eMMC(50MHz x8)"; 816 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) 817 const char *boot_hyper160 = "HyperFlash(150MHz)"; 818 #else 819 const char *boot_hyper160 = "HyperFlash(160MHz)"; 820 #endif 821 #if (RCAR_LOSSY_ENABLE == 1) 822 int fcnlnode; 823 #endif 824 825 bl2_init_generic_timer(); 826 827 reg = mmio_read_32(RCAR_MODEMR); 828 boot_dev = reg & MODEMR_BOOT_DEV_MASK; 829 boot_cpu = reg & MODEMR_BOOT_CPU_MASK; 830 831 bl2_cpg_init(); 832 833 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 834 boot_cpu == MODEMR_BOOT_CPU_CA53) { 835 rcar_pfc_init(); 836 rcar_console_boot_init(); 837 } 838 839 plat_rcar_gic_driver_init(); 840 plat_rcar_gic_init(); 841 rcar_swdt_init(); 842 843 /* FIQ interrupts are taken to EL3 */ 844 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT); 845 846 write_daifclr(DAIF_FIQ_BIT); 847 848 reg = read_midr(); 849 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); 850 switch (midr) { 851 case MIDR_CA57: 852 str = cpu_ca57; 853 break; 854 case MIDR_CA53: 855 str = cpu_ca53; 856 break; 857 default: 858 str = unknown; 859 break; 860 } 861 862 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str, 863 version_of_renesas); 864 865 reg = mmio_read_32(RCAR_PRR); 866 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 867 product = reg & PRR_PRODUCT_MASK; 868 869 switch (product) { 870 case PRR_PRODUCT_H3: 871 str = product_h3; 872 break; 873 case PRR_PRODUCT_M3: 874 str = product_m3; 875 break; 876 case PRR_PRODUCT_M3N: 877 str = product_m3n; 878 break; 879 case PRR_PRODUCT_V3M: 880 str = product_v3m; 881 break; 882 case PRR_PRODUCT_E3: 883 str = product_e3; 884 break; 885 case PRR_PRODUCT_D3: 886 str = product_d3; 887 break; 888 default: 889 str = unknown; 890 break; 891 } 892 893 if ((PRR_PRODUCT_M3 == product) && 894 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) { 895 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 896 /* M3 Ver.1.1 or Ver.1.2 */ 897 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", 898 str); 899 } else { 900 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n", 901 str, 902 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET); 903 } 904 } else if (product == PRR_PRODUCT_D3) { 905 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) { 906 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str); 907 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) { 908 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str); 909 } else { 910 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str); 911 } 912 } else { 913 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT; 914 major = major + RCAR_MAJOR_OFFSET; 915 minor = reg & RCAR_MINOR_MASK; 916 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); 917 } 918 919 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) { 920 reg = mmio_read_32(RCAR_MODEMR); 921 sscg = reg & RCAR_SSCG_MASK; 922 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; 923 NOTICE("BL2: %s\n", str); 924 } 925 926 rcar_get_board_type(&type, &rev); 927 928 switch (type) { 929 case BOARD_SALVATOR_X: 930 case BOARD_KRIEK: 931 case BOARD_STARTER_KIT: 932 case BOARD_SALVATOR_XS: 933 case BOARD_EBISU: 934 case BOARD_STARTER_KIT_PRE: 935 case BOARD_EBISU_4D: 936 case BOARD_DRAAK: 937 case BOARD_EAGLE: 938 break; 939 default: 940 type = BOARD_UNKNOWN; 941 break; 942 } 943 944 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) 945 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type)); 946 else { 947 NOTICE("BL2: Board is %s Rev.%d.%d\n", 948 GET_BOARD_NAME(type), 949 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev)); 950 } 951 952 #if RCAR_LSI != RCAR_AUTO 953 if (product != TARGET_PRODUCT) { 954 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME); 955 ERROR("BL2: Please write the correct IPL to flash memory.\n"); 956 panic(); 957 } 958 #endif 959 rcar_avs_init(); 960 rcar_avs_setting(); 961 962 switch (boot_dev) { 963 case MODEMR_BOOT_DEV_HYPERFLASH160: 964 str = boot_hyper160; 965 break; 966 case MODEMR_BOOT_DEV_HYPERFLASH80: 967 str = boot_hyper80; 968 break; 969 case MODEMR_BOOT_DEV_QSPI_FLASH40: 970 str = boot_qspi40; 971 break; 972 case MODEMR_BOOT_DEV_QSPI_FLASH80: 973 str = boot_qspi80; 974 break; 975 case MODEMR_BOOT_DEV_EMMC_25X1: 976 #if RCAR_LSI == RCAR_D3 977 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n"); 978 panic(); 979 #endif 980 str = boot_emmc25x1; 981 break; 982 case MODEMR_BOOT_DEV_EMMC_50X8: 983 str = boot_emmc50x8; 984 break; 985 default: 986 str = unknown; 987 break; 988 } 989 NOTICE("BL2: Boot device is %s\n", str); 990 991 rcar_avs_setting(); 992 reg = rcar_rom_get_lcs(&lcs); 993 if (reg) { 994 str = unknown; 995 goto lcm_state; 996 } 997 998 switch (lcs) { 999 case LCS_CM: 1000 str = lcs_cm; 1001 break; 1002 case LCS_DM: 1003 str = lcs_dm; 1004 break; 1005 case LCS_SD: 1006 str = lcs_sd; 1007 break; 1008 case LCS_SE: 1009 str = lcs_secure; 1010 break; 1011 case LCS_FA: 1012 str = lcs_fa; 1013 break; 1014 default: 1015 str = unknown; 1016 break; 1017 } 1018 1019 lcm_state: 1020 NOTICE("BL2: LCM state is %s\n", str); 1021 1022 rcar_avs_end(); 1023 is_ddr_backup_mode(); 1024 1025 bl2_tzram_layout.total_base = BL31_BASE; 1026 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; 1027 1028 if (boot_cpu == MODEMR_BOOT_CPU_CA57 || 1029 boot_cpu == MODEMR_BOOT_CPU_CA53) { 1030 ret = rcar_dram_init(); 1031 if (ret) { 1032 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret); 1033 panic(); 1034 } 1035 rcar_qos_init(); 1036 } 1037 1038 /* Set up FDT */ 1039 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob)); 1040 if (ret) { 1041 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret); 1042 panic(); 1043 } 1044 1045 /* Add platform compatible string */ 1046 bl2_populate_compatible_string(fdt); 1047 1048 /* Enable RPC if unlocked */ 1049 bl2_add_rpc_node(); 1050 1051 /* Print DRAM layout */ 1052 bl2_advertise_dram_size(product); 1053 1054 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1055 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) { 1056 if (rcar_emmc_init() != EMMC_SUCCESS) { 1057 NOTICE("BL2: Failed to eMMC driver initialize.\n"); 1058 panic(); 1059 } 1060 rcar_emmc_memcard_power(EMMC_POWER_ON); 1061 if (rcar_emmc_mount() != EMMC_SUCCESS) { 1062 NOTICE("BL2: Failed to eMMC mount operation.\n"); 1063 panic(); 1064 } 1065 } else { 1066 rcar_rpc_init(); 1067 rcar_dma_init(); 1068 } 1069 1070 reg = mmio_read_32(RST_WDTRSTCR); 1071 reg &= ~WDTRSTCR_RWDT_RSTMSK; 1072 reg |= WDTRSTCR_PASSWORD; 1073 mmio_write_32(RST_WDTRSTCR, reg); 1074 1075 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); 1076 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); 1077 1078 reg = mmio_read_32(RCAR_PRR); 1079 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) 1080 mmio_write_32(CPG_CA57DBGRCR, 1081 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); 1082 1083 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) 1084 mmio_write_32(CPG_CA53DBGRCR, 1085 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); 1086 1087 if (product_cut == PRR_PRODUCT_H3_CUT10) { 1088 reg = mmio_read_32(CPG_PLL2CR); 1089 reg &= ~((uint32_t) 1 << 5); 1090 mmio_write_32(CPG_PLL2CR, reg); 1091 1092 reg = mmio_read_32(CPG_PLL4CR); 1093 reg &= ~((uint32_t) 1 << 5); 1094 mmio_write_32(CPG_PLL4CR, reg); 1095 1096 reg = mmio_read_32(CPG_PLL0CR); 1097 reg &= ~((uint32_t) 1 << 12); 1098 mmio_write_32(CPG_PLL0CR, reg); 1099 } 1100 #if (RCAR_LOSSY_ENABLE == 1) 1101 NOTICE("BL2: Lossy Decomp areas\n"); 1102 1103 fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory"); 1104 if (fcnlnode < 0) { 1105 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n", 1106 fcnlnode); 1107 panic(); 1108 } 1109 1110 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, 1111 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode); 1112 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, 1113 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode); 1114 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, 1115 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode); 1116 #endif 1117 1118 fdt_pack(fdt); 1119 NOTICE("BL2: FDT at %p\n", fdt); 1120 1121 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 || 1122 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) 1123 rcar_io_emmc_setup(); 1124 else 1125 rcar_io_setup(); 1126 } 1127 1128 void bl2_el3_plat_arch_setup(void) 1129 { 1130 #if RCAR_BL2_DCACHE == 1 1131 NOTICE("BL2: D-Cache enable\n"); 1132 rcar_configure_mmu_el3(BL2_BASE, 1133 BL2_END - BL2_BASE, 1134 BL2_RO_BASE, BL2_RO_LIMIT 1135 #if USE_COHERENT_MEM 1136 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT 1137 #endif 1138 ); 1139 #endif 1140 } 1141 1142 void bl2_platform_setup(void) 1143 { 1144 1145 } 1146 1147 static void bl2_init_generic_timer(void) 1148 { 1149 /* FIXME: V3M 16.666 MHz ? */ 1150 #if RCAR_LSI == RCAR_D3 1151 uint32_t reg_cntfid = EXTAL_DRAAK; 1152 #elif RCAR_LSI == RCAR_E3 1153 uint32_t reg_cntfid = EXTAL_EBISU; 1154 #else /* RCAR_LSI == RCAR_E3 */ 1155 uint32_t reg; 1156 uint32_t reg_cntfid; 1157 uint32_t modemr; 1158 uint32_t modemr_pll; 1159 uint32_t board_type; 1160 uint32_t board_rev; 1161 uint32_t pll_table[] = { 1162 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */ 1163 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */ 1164 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */ 1165 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */ 1166 }; 1167 1168 modemr = mmio_read_32(RCAR_MODEMR); 1169 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); 1170 1171 /* Set frequency data in CNTFID0 */ 1172 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; 1173 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 1174 switch (modemr_pll) { 1175 case MD14_MD13_TYPE_0: 1176 rcar_get_board_type(&board_type, &board_rev); 1177 if (BOARD_SALVATOR_XS == board_type) { 1178 reg_cntfid = EXTAL_SALVATOR_XS; 1179 } 1180 break; 1181 case MD14_MD13_TYPE_3: 1182 if (PRR_PRODUCT_H3_CUT10 == reg) { 1183 reg_cntfid = reg_cntfid >> 1U; 1184 } 1185 break; 1186 default: 1187 /* none */ 1188 break; 1189 } 1190 #endif /* RCAR_LSI == RCAR_E3 */ 1191 /* Update memory mapped and register based freqency */ 1192 write_cntfrq_el0((u_register_t )reg_cntfid); 1193 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); 1194 /* Enable counter */ 1195 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, 1196 (uint32_t)CNTCR_EN); 1197 } 1198