1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/cci.h> 16 #include <drivers/console.h> 17 #include <lib/mmio.h> 18 #include <plat/common/platform.h> 19 20 #include "pwrc.h" 21 #include "timer.h" 22 23 #include "rcar_def.h" 24 #include "rcar_private.h" 25 #include "rcar_version.h" 26 27 static const uint64_t BL31_RO_BASE = BL_CODE_BASE; 28 static const uint64_t BL31_RO_LIMIT = BL_CODE_END; 29 30 #if USE_COHERENT_MEM 31 static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE; 32 static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END; 33 #endif /* USE_COHERENT_MEM */ 34 35 extern void plat_rcar_gic_driver_init(void); 36 extern void plat_rcar_gic_init(void); 37 38 u_register_t rcar_boot_mpidr; 39 40 static int cci_map[] = { 41 CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3, 42 CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 43 }; 44 45 void plat_cci_init(void) 46 { 47 uint32_t prd; 48 49 prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK); 50 51 if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) { 52 cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX; 53 cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX; 54 } 55 56 cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 57 } 58 59 void plat_cci_enable(void) 60 { 61 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 62 } 63 64 void plat_cci_disable(void) 65 { 66 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 67 } 68 69 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 70 { 71 bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *) 72 PARAMS_BASE; 73 entry_point_info_t *next_image_info; 74 75 next_image_info = (type == NON_SECURE) ? 76 &from_bl2->bl33_ep_info : &from_bl2->bl32_ep_info; 77 78 return next_image_info->pc ? next_image_info : NULL; 79 } 80 81 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 82 u_register_t arg2, u_register_t arg3) 83 { 84 rcar_console_runtime_init(); 85 86 NOTICE("BL3-1 : Rev.%s\n", version_of_renesas); 87 88 #if RCAR_LSI != RCAR_D3 89 if (rcar_pwrc_get_cluster() == RCAR_CLUSTER_A53A57) { 90 plat_cci_init(); 91 plat_cci_enable(); 92 } 93 #endif /* RCAR_LSI != RCAR_D3 */ 94 } 95 96 void bl31_plat_arch_setup(void) 97 { 98 rcar_configure_mmu_el3(BL31_BASE, 99 BL31_LIMIT - BL31_BASE, 100 BL31_RO_BASE, BL31_RO_LIMIT 101 #if USE_COHERENT_MEM 102 , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT 103 #endif /* USE_COHERENT_MEM */ 104 ); 105 rcar_pwrc_code_copy_to_system_ram(); 106 } 107 108 void bl31_platform_setup(void) 109 { 110 plat_rcar_gic_driver_init(); 111 plat_rcar_gic_init(); 112 113 /* enable the system level generic timer */ 114 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN); 115 116 rcar_pwrc_setup(); 117 #if 0 118 /* 119 * TODO: there is a broad number of rcar-gen3 SoC configurations; to 120 * support all of them, Renesas use the pwrc driver to discover what 121 * cores are on/off before announcing the topology. 122 * This code hasnt been ported yet 123 */ 124 125 rcar_setup_topology(); 126 #endif 127 128 /* 129 * mask should match the kernel's MPIDR_HWID_BITMASK so the core can be 130 * identified during cpuhotplug (check the kernel's psci migrate set of 131 * functions 132 */ 133 rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU; 134 rcar_pwrc_all_disable_interrupt_wakeup(); 135 } 136