1 /*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <platform_def.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/interrupt_props.h>
15 #include <drivers/arm/gicv2.h>
16 #include <drivers/arm/gic_common.h>
17 #include <lib/mmio.h>
18 #include <lib/xlat_tables/xlat_tables_v2.h>
19 #include <plat/common/platform.h>
20
21 #include "rcar_def.h"
22 #include "rcar_private.h"
23 #include "rcar_version.h"
24
25 #if (IMAGE_BL2)
26 extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
27 extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
28 #endif
29
30 const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
31 __attribute__ ((__section__(".ro"))) = VERSION_OF_RENESAS;
32
33 #if (IMAGE_BL2) && (RCAR_BL2_DCACHE != 1)
34 #define RCAR_DCACHE MT_NON_CACHEABLE
35 #else
36 #define RCAR_DCACHE MT_MEMORY
37 #endif
38
39 #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
40 RCAR_SHARED_MEM_SIZE, \
41 MT_MEMORY | MT_RW | MT_SECURE)
42
43 #define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
44 FLASH0_SIZE, \
45 RCAR_DCACHE | MT_RO | MT_SECURE)
46
47 #define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
48 DRAM1_NS_SIZE, \
49 MT_MEMORY | MT_RW | MT_NS)
50
51 #define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
52 DEVICE_RCAR_SIZE, \
53 MT_DEVICE | MT_RW | MT_SECURE)
54
55 #define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
56 DEVICE_RCAR_SIZE2, \
57 MT_DEVICE | MT_RW | MT_SECURE)
58
59 #define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
60 DEVICE_SRAM_SIZE, \
61 MT_MEMORY | MT_RO | MT_SECURE)
62
63 #define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
64 DEVICE_SRAM_STACK_SIZE, \
65 MT_MEMORY | MT_RW | MT_SECURE)
66
67 #define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
68 RCAR_BL31_CRASH_SIZE, \
69 MT_MEMORY | MT_RW | MT_SECURE)
70
71 #define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
72 RCAR_BL31_LOG_SIZE, \
73 MT_DEVICE | MT_RW | MT_SECURE)
74 #if IMAGE_BL2
75 #define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
76 DRAM1_SIZE, \
77 RCAR_DCACHE | MT_RW | MT_SECURE)
78
79 #define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
80 DEVICE_RCAR_SIZE, \
81 MT_DEVICE | MT_RW | MT_SECURE)
82
83 #define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
84 RCAR_SYSRAM_SIZE, \
85 RCAR_DCACHE | MT_RW | MT_SECURE)
86
87 #define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
88 REG1_SIZE, \
89 MT_DEVICE | MT_RW | MT_SECURE)
90
91 #define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
92 ROM0_SIZE, \
93 RCAR_DCACHE | MT_RO | MT_SECURE)
94
95 #define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
96 REG2_SIZE, \
97 MT_DEVICE | MT_RW | MT_SECURE)
98
99 #define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
100 DRAM_40BIT_SIZE, \
101 RCAR_DCACHE | MT_RW | MT_SECURE)
102 #endif
103
104 #ifdef BL32_BASE
105 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \
106 BL32_LIMIT - BL32_BASE, \
107 MT_MEMORY | MT_RW | MT_SECURE)
108 #endif
109
110 #if IMAGE_BL2
111 static const mmap_region_t rcar_mmap[] = {
112 MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
113 MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
114 MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
115 MAP_RAM0, /* 0xE6300000 - 0xE6303FFF System RAM area */
116 MAP_REG1, /* 0xE6400000 - 0xEAFFFFFF SoC register area */
117 MAP_ROM, /* 0xEB100000 - 0xEB127FFF boot ROM area */
118 MAP_REG2, /* 0xEC000000 - 0xFFFFFFFF SoC register area */
119 MAP_DRAM1, /* 0x0400000000 - 0x07FFFFFFFF DRAM area(4GB over) */
120 {0}
121 };
122 #endif
123
124 #if IMAGE_BL31
125 static const mmap_region_t rcar_mmap[] = {
126 MAP_SHARED_RAM,
127 MAP_ATFW_CRASH,
128 MAP_ATFW_LOG,
129 MAP_DEVICE_RCAR,
130 MAP_DEVICE_RCAR2,
131 MAP_SRAM,
132 MAP_SRAM_STACK,
133 {0}
134 };
135 #endif
136
137 #if IMAGE_BL32
138 static const mmap_region_t rcar_mmap[] = {
139 MAP_DEVICE0,
140 MAP_DEVICE1,
141 {0}
142 };
143 #endif
144
145 CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
146 <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
147
148 /*
149 * Macro generating the code for the function setting up the pagetables as per
150 * the platform memory map & initialize the mmu, for the given exception level
151 */
152 #if USE_COHERENT_MEM
rcar_configure_mmu_el3(unsigned long total_base,unsigned long total_size,unsigned long ro_start,unsigned long ro_limit,unsigned long coh_start,unsigned long coh_limit)153 void rcar_configure_mmu_el3(unsigned long total_base,
154 unsigned long total_size,
155 unsigned long ro_start,
156 unsigned long ro_limit,
157 unsigned long coh_start,
158 unsigned long coh_limit)
159 {
160 mmap_add_region(total_base, total_base, total_size,
161 RCAR_DCACHE | MT_RW | MT_SECURE);
162 mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
163 RCAR_DCACHE | MT_RO | MT_SECURE);
164 mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
165 MT_DEVICE | MT_RW | MT_SECURE);
166 mmap_add(rcar_mmap);
167
168 init_xlat_tables();
169 enable_mmu_el3(0);
170 }
171 #else
rcar_configure_mmu_el3(unsigned long total_base,unsigned long total_size,unsigned long ro_start,unsigned long ro_limit)172 void rcar_configure_mmu_el3(unsigned long total_base,
173 unsigned long total_size,
174 unsigned long ro_start,
175 unsigned long ro_limit)
176 {
177 mmap_add_region(total_base, total_base, total_size,
178 RCAR_DCACHE | MT_RW | MT_SECURE);
179 mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
180 RCAR_DCACHE | MT_RO | MT_SECURE);
181 mmap_add(rcar_mmap);
182
183 init_xlat_tables();
184 enable_mmu_el3(0);
185 }
186 #endif
187
plat_get_ns_image_entrypoint(void)188 uintptr_t plat_get_ns_image_entrypoint(void)
189 {
190 #if (IMAGE_BL2)
191 uint32_t cert, len;
192 uintptr_t dst;
193 int32_t ret;
194
195 ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
196 if (ret) {
197 ERROR("%s : cert file load error", __func__);
198 return NS_IMAGE_OFFSET;
199 }
200
201 rcar_read_certificate((uint64_t) cert, &len, &dst);
202
203 return dst;
204 #else
205 return NS_IMAGE_OFFSET;
206 #endif
207 }
208
plat_get_syscnt_freq2(void)209 unsigned int plat_get_syscnt_freq2(void)
210 {
211 unsigned int freq;
212
213 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
214 if (freq == 0)
215 panic();
216
217 return freq;
218 }
219
plat_rcar_gic_init(void)220 void plat_rcar_gic_init(void)
221 {
222 gicv2_distif_init();
223 gicv2_pcpu_distif_init();
224 gicv2_cpuif_enable();
225 }
226
227 static const interrupt_prop_t interrupt_props[] = {
228 #if IMAGE_BL2
229 INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
230 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
231 #else
232 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
233 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
234 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
235 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
236 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
238 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
240 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
242 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
243 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
244 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
245 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
246 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
247 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
248 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
249 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
250 INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
251 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
252 INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
253 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
254 INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
255 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
256 INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
257 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
258 INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
259 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
260 INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
261 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
262 INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
263 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
264 #endif
265 };
266
267 static const gicv2_driver_data_t plat_gicv2_driver_data = {
268 .interrupt_props = interrupt_props,
269 .interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
270 .gicd_base = RCAR_GICD_BASE,
271 .gicc_base = RCAR_GICC_BASE,
272 };
273
plat_rcar_gic_driver_init(void)274 void plat_rcar_gic_driver_init(void)
275 {
276 gicv2_driver_init(&plat_gicv2_driver_data);
277 }
278