1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common_def.h> 11 12 #include <qti_board_def.h> 13 #include <qtiseclib_defs_plat.h> 14 15 /*----------------------------------------------------------------------------*/ 16 17 /*----------------------------------------------------------------------------*/ 18 /* 19 * MPIDR_PRIMARY_CPU 20 * You just need to have the correct core_affinity_val i.e. [7:0] 21 * and cluster_affinity_val i.e. [15:8] 22 * the other bits will be ignored 23 */ 24 /*----------------------------------------------------------------------------*/ 25 #define MPIDR_PRIMARY_CPU 0x0000 26 /*----------------------------------------------------------------------------*/ 27 28 #define QTI_PWR_LVL0 MPIDR_AFFLVL0 29 #define QTI_PWR_LVL1 MPIDR_AFFLVL1 30 #define QTI_PWR_LVL2 MPIDR_AFFLVL2 31 #define QTI_PWR_LVL3 MPIDR_AFFLVL3 32 33 /* 34 * Macros for local power states encoded by State-ID field 35 * within the power-state parameter. 36 */ 37 /* Local power state for power domains in Run state. */ 38 #define QTI_LOCAL_STATE_RUN 0 39 /* 40 * Local power state for clock-gating. Valid only for CPU and not cluster power 41 * domains 42 */ 43 #define QTI_LOCAL_STATE_STB 1 44 /* 45 * Local power state for retention. Valid for CPU and cluster power 46 * domains 47 */ 48 #define QTI_LOCAL_STATE_RET 2 49 /* 50 * Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC 51 * power domains 52 */ 53 #define QTI_LOCAL_STATE_OFF 3 54 /* 55 * Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC 56 * power domains 57 */ 58 #define QTI_LOCAL_STATE_DEEPOFF 4 59 60 /* 61 * This macro defines the deepest retention state possible. A higher state 62 * id will represent an invalid or a power down state. 63 */ 64 #define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET 65 66 /* 67 * This macro defines the deepest power down states possible. Any state ID 68 * higher than this is invalid. 69 */ 70 #define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF 71 72 /****************************************************************************** 73 * Required platform porting definitions common to all ARM standard platforms 74 *****************************************************************************/ 75 76 /* 77 * Platform specific page table and MMU setup constants. 78 */ 79 #define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES) 80 81 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36) 82 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36) 83 84 #define ARM_CACHE_WRITEBACK_SHIFT 6 85 86 /* 87 * Some data must be aligned on the biggest cache line size in the platform. 88 * This is known only to the platform as it might have a combination of 89 * integrated and external caches. 90 */ 91 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 92 93 /* 94 * One cache line needed for bakery locks on ARM platforms 95 */ 96 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 97 98 /*----------------------------------------------------------------------------*/ 99 /* PSCI power domain topology definitions */ 100 /*----------------------------------------------------------------------------*/ 101 /* One domain each to represent RSC and PDC level */ 102 #define PLAT_PDC_COUNT 1 103 #define PLAT_RSC_COUNT 1 104 105 /* There is one top-level FCM cluster */ 106 #define PLAT_CLUSTER_COUNT 1 107 108 /* No. of cores in the FCM cluster */ 109 #define PLAT_CLUSTER0_CORE_COUNT 8 110 111 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT) 112 113 #define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\ 114 PLAT_RSC_COUNT +\ 115 PLAT_CLUSTER_COUNT +\ 116 PLATFORM_CORE_COUNT) 117 118 #define PLAT_MAX_PWR_LVL 3 119 120 /*****************************************************************************/ 121 /* Memory mapped Generic timer interfaces */ 122 /*****************************************************************************/ 123 124 /*----------------------------------------------------------------------------*/ 125 /* GIC-600 constants */ 126 /*----------------------------------------------------------------------------*/ 127 #define BASE_GICD_BASE 0x17A00000 128 #define BASE_GICR_BASE 0x17A60000 129 #define BASE_GICC_BASE 0x0 130 #define BASE_GICH_BASE 0x0 131 #define BASE_GICV_BASE 0x0 132 133 #define QTI_GICD_BASE BASE_GICD_BASE 134 #define QTI_GICR_BASE BASE_GICR_BASE 135 #define QTI_GICC_BASE BASE_GICC_BASE 136 137 /*----------------------------------------------------------------------------*/ 138 139 /*----------------------------------------------------------------------------*/ 140 /* UART related constants. */ 141 /*----------------------------------------------------------------------------*/ 142 #define PLAT_QTI_UART_BASE 0xa80000 143 /* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */ 144 #define GENI4_CFG 0x0 145 #define GENI4_IMAGE_REGS 0x100 146 #define GENI4_DATA 0x600 147 148 /* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ 149 #define GENI_STATUS_REG (GENI4_CFG + 0x00000040) 150 #define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1) 151 #define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170) 152 /* MASTER/TX ENGINE REGISTERS */ 153 #define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000) 154 /* FIFO, STATUS REGISTERS AND MASKS */ 155 #define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100) 156 157 #define GENI_M_CMD_TX (0x08000000) 158 159 /*----------------------------------------------------------------------------*/ 160 /* Peripherals base addresses */ 161 /*----------------------------------------------------------------------------*/ 162 #define QTI_SEC_PRNG_BASE 0x790000 163 164 /*----------------------------------------------------------------------------*/ 165 /* Device address space for mapping. Excluding starting 4K */ 166 /*----------------------------------------------------------------------------*/ 167 #define QTI_DEVICE_BASE 0x1000 168 #define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE) 169 170 /******************************************************************************* 171 * BL31 specific defines. 172 ******************************************************************************/ 173 /* 174 * Put BL31 at DDR as per memory map. BL31_BASE is calculated using the 175 * current BL31 debug size plus a little space for growth. 176 */ 177 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 178 179 /*----------------------------------------------------------------------------*/ 180 /* AOSS registers */ 181 /*----------------------------------------------------------------------------*/ 182 #define QTI_PS_HOLD_REG 0x0C264000 183 /*----------------------------------------------------------------------------*/ 184 /* AOP CMD DB address space for mapping */ 185 /*----------------------------------------------------------------------------*/ 186 #define QTI_AOP_CMD_DB_BASE 0x80820000 187 #define QTI_AOP_CMD_DB_SIZE 0x00020000 188 /*----------------------------------------------------------------------------*/ 189 /* SOC hw version register */ 190 /*----------------------------------------------------------------------------*/ 191 #define QTI_SOC_VERSION_MASK U(0xFFFF) 192 #define QTI_SOC_REVISION_REG 0x1FC8000 193 #define QTI_SOC_REVISION_MASK U(0xFFFF) 194 /*----------------------------------------------------------------------------*/ 195 /* LC PON register offsets */ 196 /*----------------------------------------------------------------------------*/ 197 #define PON_PS_HOLD_RESET_CTL 0x85a 198 #define PON_PS_HOLD_RESET_CTL2 0x85b 199 /*----------------------------------------------------------------------------*/ 200 201 #endif /* PLATFORM_DEF_H */ 202