15bd9c17dSSaurabh Gorecha /* 25bd9c17dSSaurabh Gorecha * Copyright (c) 2020, The Linux Foundation. All rights reserved. 35bd9c17dSSaurabh Gorecha * 45bd9c17dSSaurabh Gorecha * SPDX-License-Identifier: BSD-3-Clause 55bd9c17dSSaurabh Gorecha */ 65bd9c17dSSaurabh Gorecha 75bd9c17dSSaurabh Gorecha #include <stdbool.h> 85bd9c17dSSaurabh Gorecha #include <stdint.h> 95bd9c17dSSaurabh Gorecha 105bd9c17dSSaurabh Gorecha #include <common/debug.h> 115bd9c17dSSaurabh Gorecha 125bd9c17dSSaurabh Gorecha #include <qtiseclib_defs.h> 135bd9c17dSSaurabh Gorecha #include <qtiseclib_interface.h> 145bd9c17dSSaurabh Gorecha 155bd9c17dSSaurabh Gorecha /* 165bd9c17dSSaurabh Gorecha * This file contains dummy implementation of QTISECLIB Published API's. 175bd9c17dSSaurabh Gorecha * which will be used to compile PLATFORM successfully when 185bd9c17dSSaurabh Gorecha * qtiseclib is not available 195bd9c17dSSaurabh Gorecha */ 205bd9c17dSSaurabh Gorecha 215bd9c17dSSaurabh Gorecha /* 225bd9c17dSSaurabh Gorecha * CPUSS common reset handler for all CPU wake up (both cold & warm boot). 235bd9c17dSSaurabh Gorecha * Executes on all core. This API assume serialization across CPU 245bd9c17dSSaurabh Gorecha * already taken care before invoking. 255bd9c17dSSaurabh Gorecha * 265bd9c17dSSaurabh Gorecha * Clobbers: x0 - x17, x30 275bd9c17dSSaurabh Gorecha */ 285bd9c17dSSaurabh Gorecha void qtiseclib_cpuss_reset_asm(uint32_t bl31_cold_boot_state) 295bd9c17dSSaurabh Gorecha { 305bd9c17dSSaurabh Gorecha } 315bd9c17dSSaurabh Gorecha 325bd9c17dSSaurabh Gorecha /* 335bd9c17dSSaurabh Gorecha * Execute CPU (Kryo4 gold) specific reset handler / system initialization. 345bd9c17dSSaurabh Gorecha * This takes care of executing required CPU errata's. 355bd9c17dSSaurabh Gorecha * 365bd9c17dSSaurabh Gorecha * Clobbers: x0 - x16 375bd9c17dSSaurabh Gorecha */ 385bd9c17dSSaurabh Gorecha void qtiseclib_kryo4_gold_reset_asm(void) 395bd9c17dSSaurabh Gorecha { 405bd9c17dSSaurabh Gorecha } 415bd9c17dSSaurabh Gorecha 425bd9c17dSSaurabh Gorecha /* 435bd9c17dSSaurabh Gorecha * Execute CPU (Kryo4 silver) specific reset handler / system initialization. 445bd9c17dSSaurabh Gorecha * This takes care of executing required CPU errata's. 455bd9c17dSSaurabh Gorecha * 465bd9c17dSSaurabh Gorecha * Clobbers: x0 - x16 475bd9c17dSSaurabh Gorecha */ 485bd9c17dSSaurabh Gorecha void qtiseclib_kryo4_silver_reset_asm(void) 495bd9c17dSSaurabh Gorecha { 505bd9c17dSSaurabh Gorecha } 515bd9c17dSSaurabh Gorecha 525bd9c17dSSaurabh Gorecha /* 53*6cc743cfSSaurabh Gorecha * Execute CPU (Kryo4 gold) specific reset handler / system initialization. 54*6cc743cfSSaurabh Gorecha * This takes care of executing required CPU errata's. 55*6cc743cfSSaurabh Gorecha * 56*6cc743cfSSaurabh Gorecha * Clobbers: x0 - x16 57*6cc743cfSSaurabh Gorecha */ 58*6cc743cfSSaurabh Gorecha void qtiseclib_kryo6_gold_reset_asm(void) 59*6cc743cfSSaurabh Gorecha { 60*6cc743cfSSaurabh Gorecha } 61*6cc743cfSSaurabh Gorecha 62*6cc743cfSSaurabh Gorecha 63*6cc743cfSSaurabh Gorecha void qtiseclib_kryo6_silver_reset_asm(void) 64*6cc743cfSSaurabh Gorecha { 65*6cc743cfSSaurabh Gorecha } 66*6cc743cfSSaurabh Gorecha 67*6cc743cfSSaurabh Gorecha /* 685bd9c17dSSaurabh Gorecha * C Api's 695bd9c17dSSaurabh Gorecha */ 705bd9c17dSSaurabh Gorecha void qtiseclib_bl31_platform_setup(void) 715bd9c17dSSaurabh Gorecha { 725bd9c17dSSaurabh Gorecha ERROR("Please use QTISECLIB_PATH while building TF-A\n"); 735bd9c17dSSaurabh Gorecha ERROR("Please refer docs/plat/qti.rst for more details.\n"); 745bd9c17dSSaurabh Gorecha panic(); 755bd9c17dSSaurabh Gorecha } 765bd9c17dSSaurabh Gorecha 775bd9c17dSSaurabh Gorecha void qtiseclib_invoke_isr(uint32_t irq, void *handle) 785bd9c17dSSaurabh Gorecha { 795bd9c17dSSaurabh Gorecha } 805bd9c17dSSaurabh Gorecha 815bd9c17dSSaurabh Gorecha void qtiseclib_panic(void) 825bd9c17dSSaurabh Gorecha { 835bd9c17dSSaurabh Gorecha } 845bd9c17dSSaurabh Gorecha 855bd9c17dSSaurabh Gorecha int 865bd9c17dSSaurabh Gorecha qtiseclib_mem_assign(const memprot_info_t *mem_info, 875bd9c17dSSaurabh Gorecha uint32_t mem_info_list_cnt, 885bd9c17dSSaurabh Gorecha const uint32_t *source_vm_list, 895bd9c17dSSaurabh Gorecha uint32_t src_vm_list_cnt, 905bd9c17dSSaurabh Gorecha const memprot_dst_vm_perm_info_t *dest_vm_list, 915bd9c17dSSaurabh Gorecha uint32_t dst_vm_list_cnt) 925bd9c17dSSaurabh Gorecha { 935bd9c17dSSaurabh Gorecha return 0; 945bd9c17dSSaurabh Gorecha } 955bd9c17dSSaurabh Gorecha 965bd9c17dSSaurabh Gorecha int qtiseclib_psci_init(uintptr_t warmboot_entry) 975bd9c17dSSaurabh Gorecha { 985bd9c17dSSaurabh Gorecha return 0; 995bd9c17dSSaurabh Gorecha } 1005bd9c17dSSaurabh Gorecha 1015bd9c17dSSaurabh Gorecha int qtiseclib_psci_node_power_on(u_register_t mpidr) 1025bd9c17dSSaurabh Gorecha { 1035bd9c17dSSaurabh Gorecha return 0; 1045bd9c17dSSaurabh Gorecha } 1055bd9c17dSSaurabh Gorecha 1065bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_on_finish(const uint8_t *states) 1075bd9c17dSSaurabh Gorecha { 1085bd9c17dSSaurabh Gorecha } 1095bd9c17dSSaurabh Gorecha 1105bd9c17dSSaurabh Gorecha void qtiseclib_psci_cpu_standby(uint8_t pwr_state) 1115bd9c17dSSaurabh Gorecha { 1125bd9c17dSSaurabh Gorecha } 1135bd9c17dSSaurabh Gorecha 1145bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_power_off(const uint8_t *states) 1155bd9c17dSSaurabh Gorecha { 1165bd9c17dSSaurabh Gorecha } 1175bd9c17dSSaurabh Gorecha 1185bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_suspend(const uint8_t *states) 1195bd9c17dSSaurabh Gorecha { 1205bd9c17dSSaurabh Gorecha } 1215bd9c17dSSaurabh Gorecha 1225bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_suspend_finish(const uint8_t *states) 1235bd9c17dSSaurabh Gorecha { 1245bd9c17dSSaurabh Gorecha } 1255bd9c17dSSaurabh Gorecha 1265bd9c17dSSaurabh Gorecha void qtiseclib_disable_cluster_coherency(uint8_t state) 1275bd9c17dSSaurabh Gorecha { 1285bd9c17dSSaurabh Gorecha } 1295bd9c17dSSaurabh Gorecha 130