15bd9c17dSSaurabh Gorecha /* 2*46ee50e0SSaurabh Gorecha * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 35bd9c17dSSaurabh Gorecha * 45bd9c17dSSaurabh Gorecha * SPDX-License-Identifier: BSD-3-Clause 55bd9c17dSSaurabh Gorecha */ 65bd9c17dSSaurabh Gorecha 75bd9c17dSSaurabh Gorecha #ifndef QTISECLIB_INTERFACE_H 85bd9c17dSSaurabh Gorecha #define QTISECLIB_INTERFACE_H 95bd9c17dSSaurabh Gorecha 105bd9c17dSSaurabh Gorecha #include <stdbool.h> 115bd9c17dSSaurabh Gorecha #include <stdint.h> 125bd9c17dSSaurabh Gorecha 135bd9c17dSSaurabh Gorecha #include <qtiseclib_defs.h> 145bd9c17dSSaurabh Gorecha 155bd9c17dSSaurabh Gorecha typedef struct memprot_ipa_info_s { 165bd9c17dSSaurabh Gorecha uint64_t mem_addr; 175bd9c17dSSaurabh Gorecha uint64_t mem_size; 185bd9c17dSSaurabh Gorecha } memprot_info_t; 195bd9c17dSSaurabh Gorecha 205bd9c17dSSaurabh Gorecha typedef struct memprot_dst_vm_perm_info_s { 215bd9c17dSSaurabh Gorecha uint32_t dst_vm; 225bd9c17dSSaurabh Gorecha uint32_t dst_vm_perm; 235bd9c17dSSaurabh Gorecha uint64_t ctx; 245bd9c17dSSaurabh Gorecha uint32_t ctx_size; 255bd9c17dSSaurabh Gorecha } memprot_dst_vm_perm_info_t; 265bd9c17dSSaurabh Gorecha 275bd9c17dSSaurabh Gorecha /* 285bd9c17dSSaurabh Gorecha * QTISECLIB Published API's. 295bd9c17dSSaurabh Gorecha */ 305bd9c17dSSaurabh Gorecha 315bd9c17dSSaurabh Gorecha /* 325bd9c17dSSaurabh Gorecha * Assembly API's 335bd9c17dSSaurabh Gorecha */ 345bd9c17dSSaurabh Gorecha 355bd9c17dSSaurabh Gorecha /* 365bd9c17dSSaurabh Gorecha * CPUSS common reset handler for all CPU wake up (both cold & warm boot). 375bd9c17dSSaurabh Gorecha * Executes on all core. This API assume serialization across CPU 385bd9c17dSSaurabh Gorecha * already taken care before invoking. 395bd9c17dSSaurabh Gorecha * 405bd9c17dSSaurabh Gorecha * Clobbers: x0 - x17, x30 415bd9c17dSSaurabh Gorecha */ 425bd9c17dSSaurabh Gorecha void qtiseclib_cpuss_reset_asm(uint32_t bl31_cold_boot_state); 435bd9c17dSSaurabh Gorecha 445bd9c17dSSaurabh Gorecha /* 455bd9c17dSSaurabh Gorecha * Execute CPU (Kryo4 gold) specific reset handler / system initialization. 465bd9c17dSSaurabh Gorecha * This takes care of executing required CPU errata's. 475bd9c17dSSaurabh Gorecha * 485bd9c17dSSaurabh Gorecha * Clobbers: x0 - x16 495bd9c17dSSaurabh Gorecha */ 505bd9c17dSSaurabh Gorecha void qtiseclib_kryo4_gold_reset_asm(void); 515bd9c17dSSaurabh Gorecha 525bd9c17dSSaurabh Gorecha /* 53*46ee50e0SSaurabh Gorecha * Execute CPU (Kryo46 gold) specific reset handler / system initialization. 54*46ee50e0SSaurabh Gorecha * This takes care of executing required CPU errata's. 55*46ee50e0SSaurabh Gorecha * 56*46ee50e0SSaurabh Gorecha * Clobbers: x0 - x16 57*46ee50e0SSaurabh Gorecha */ 58*46ee50e0SSaurabh Gorecha void qtiseclib_kryo6_gold_reset_asm(void); 59*46ee50e0SSaurabh Gorecha 60*46ee50e0SSaurabh Gorecha /* 615bd9c17dSSaurabh Gorecha * Execute CPU (Kryo4 silver) specific reset handler / system initialization. 625bd9c17dSSaurabh Gorecha * This takes care of executing required CPU errata's. 635bd9c17dSSaurabh Gorecha * 645bd9c17dSSaurabh Gorecha * Clobbers: x0 - x16 655bd9c17dSSaurabh Gorecha */ 665bd9c17dSSaurabh Gorecha void qtiseclib_kryo4_silver_reset_asm(void); 675bd9c17dSSaurabh Gorecha 685bd9c17dSSaurabh Gorecha /* 69*46ee50e0SSaurabh Gorecha * Execute CPU (Kryo6 silver) specific reset handler / system initialization. 70*46ee50e0SSaurabh Gorecha * This takes care of executing required CPU errata's. 71*46ee50e0SSaurabh Gorecha * 72*46ee50e0SSaurabh Gorecha * Clobbers: x0 - x16 73*46ee50e0SSaurabh Gorecha */ 74*46ee50e0SSaurabh Gorecha void qtiseclib_kryo6_silver_reset_asm(void); 75*46ee50e0SSaurabh Gorecha 76*46ee50e0SSaurabh Gorecha /* 775bd9c17dSSaurabh Gorecha * C Api's 785bd9c17dSSaurabh Gorecha */ 795bd9c17dSSaurabh Gorecha void qtiseclib_bl31_platform_setup(void); 805bd9c17dSSaurabh Gorecha void qtiseclib_invoke_isr(uint32_t irq, void *handle); 815bd9c17dSSaurabh Gorecha void qtiseclib_panic(void); 825bd9c17dSSaurabh Gorecha 835bd9c17dSSaurabh Gorecha int qtiseclib_mem_assign(const memprot_info_t *mem_info, 845bd9c17dSSaurabh Gorecha uint32_t mem_info_list_cnt, 855bd9c17dSSaurabh Gorecha const uint32_t *source_vm_list, 865bd9c17dSSaurabh Gorecha uint32_t src_vm_list_cnt, 875bd9c17dSSaurabh Gorecha const memprot_dst_vm_perm_info_t *dest_vm_list, 885bd9c17dSSaurabh Gorecha uint32_t dst_vm_list_cnt); 895bd9c17dSSaurabh Gorecha 905bd9c17dSSaurabh Gorecha int qtiseclib_psci_init(uintptr_t warmboot_entry); 915bd9c17dSSaurabh Gorecha int qtiseclib_psci_node_power_on(u_register_t mpidr); 925bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_on_finish(const uint8_t *states); 935bd9c17dSSaurabh Gorecha void qtiseclib_psci_cpu_standby(uint8_t pwr_state); 945bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_power_off(const uint8_t *states); 955bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_suspend(const uint8_t *states); 965bd9c17dSSaurabh Gorecha void qtiseclib_psci_node_suspend_finish(const uint8_t *states); 975bd9c17dSSaurabh Gorecha void qtiseclib_disable_cluster_coherency(uint8_t state); 985bd9c17dSSaurabh Gorecha 995bd9c17dSSaurabh Gorecha #endif /* QTISECLIB_INTERFACE_H */ 100