1*f60617d3Squic_assethi# 2*f60617d3Squic_assethi# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3*f60617d3Squic_assethi# Copyright (c) 2024, The Linux Foundation. All rights reserved. 4*f60617d3Squic_assethi# 5*f60617d3Squic_assethi# SPDX-License-Identifier: BSD-3-Clause 6*f60617d3Squic_assethi# 7*f60617d3Squic_assethi 8*f60617d3Squic_assethi# Makefile for QCS615 QTI platform. 9*f60617d3Squic_assethi 10*f60617d3Squic_assethiQTI_PLAT_PATH := plat/qti 11*f60617d3Squic_assethiCHIPSET := ${PLAT} 12*f60617d3Squic_assethi 13*f60617d3Squic_assethi# Turn On Separate code & data. 14*f60617d3Squic_assethiSEPARATE_CODE_AND_RODATA := 1 15*f60617d3Squic_assethiUSE_COHERENT_MEM := 0 16*f60617d3Squic_assethiWARMBOOT_ENABLE_DCACHE_EARLY := 1 17*f60617d3Squic_assethiHW_ASSISTED_COHERENCY := 1 18*f60617d3Squic_assethi 19*f60617d3Squic_assethi# Enable errata configs for cortex_a76 and cortex_a55 20*f60617d3Squic_assethi# QCS615 CPU core revisions are r1p0 21*f60617d3Squic_assethiERRATA_A55_1221012 := 1 22*f60617d3Squic_assethiERRATA_A55_1530923 := 1 23*f60617d3Squic_assethiERRATA_A76_1073348 := 1 24*f60617d3Squic_assethiERRATA_A76_1130799 := 1 25*f60617d3Squic_assethiERRATA_A76_1220197 := 1 26*f60617d3Squic_assethiERRATA_A76_1257314 := 1 27*f60617d3Squic_assethiERRATA_A76_1262606 := 1 28*f60617d3Squic_assethiERRATA_A76_1262888 := 1 29*f60617d3Squic_assethiERRATA_A76_1275112 := 1 30*f60617d3Squic_assethiERRATA_A76_1791580 := 1 31*f60617d3Squic_assethiERRATA_A76_1165522 := 1 32*f60617d3Squic_assethiERRATA_A76_1868343 := 1 33*f60617d3Squic_assethiERRATA_A76_1946160 := 1 34*f60617d3Squic_assethiERRATA_A76_2743102 := 1 35*f60617d3Squic_assethi 36*f60617d3Squic_assethi# Disable the PSCI platform compatibility layer 37*f60617d3Squic_assethiENABLE_PLAT_COMPAT := 0 38*f60617d3Squic_assethi 39*f60617d3Squic_assethi# Enable PSCI v1.0 extended state ID format 40*f60617d3Squic_assethiPSCI_EXTENDED_STATE_ID := 1 41*f60617d3Squic_assethiARM_RECOM_STATE_ID_ENC := 1 42*f60617d3Squic_assethiPSCI_OS_INIT_MODE := 1 43*f60617d3Squic_assethi 44*f60617d3Squic_assethiCOLD_BOOT_SINGLE_CPU := 1 45*f60617d3Squic_assethiPROGRAMMABLE_RESET_ADDRESS := 1 46*f60617d3Squic_assethi 47*f60617d3Squic_assethiRESET_TO_BL31 := 0 48*f60617d3Squic_assethi 49*f60617d3Squic_assethiQTI_SDI_BUILD := 0 50*f60617d3Squic_assethi$(eval $(call assert_boolean,QTI_SDI_BUILD)) 51*f60617d3Squic_assethi$(eval $(call add_define,QTI_SDI_BUILD)) 52*f60617d3Squic_assethi 53*f60617d3Squic_assethi#disable CTX_INCLUDE_AARCH32_REGS to support QCS615 gold cores 54*f60617d3Squic_assethioverride CTX_INCLUDE_AARCH32_REGS := 0 55*f60617d3Squic_assethi 56*f60617d3Squic_assethi# Set dynamic CVE_2018_3639 explicitly as it defaults to 0. 57*f60617d3Squic_assethi# Others which are applicable: CVE_2017_5715 & CVE_2022_23960 default to 1 58*f60617d3Squic_assethiDYNAMIC_WORKAROUND_CVE_2018_3639 := 1 59*f60617d3Squic_assethi 60*f60617d3Squic_assethi# Enable stack protector. 61*f60617d3Squic_assethiENABLE_STACK_PROTECTOR := strong 62*f60617d3Squic_assethi 63*f60617d3Squic_assethi 64*f60617d3Squic_assethiQTI_EXTERNAL_INCLUDES := -I${QTI_PLAT_PATH}/${CHIPSET}/inc \ 65*f60617d3Squic_assethi -I${QTI_PLAT_PATH}/common/inc \ 66*f60617d3Squic_assethi -I${QTI_PLAT_PATH}/common/inc/$(ARCH) \ 67*f60617d3Squic_assethi -I${QTI_PLAT_PATH}/qtiseclib/inc \ 68*f60617d3Squic_assethi -I${QTI_PLAT_PATH}/qtiseclib/inc/${CHIPSET} \ 69*f60617d3Squic_assethi 70*f60617d3Squic_assethiQTI_BL31_SOURCES := $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_helpers.S \ 71*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_silver.S \ 72*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_gold.S \ 73*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_uart_console.S \ 74*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/pm_ps_hold.c \ 75*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_stack_protector.c \ 76*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_common.c \ 77*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_bl31_setup.c \ 78*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_gic_v3.c \ 79*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_interrupt_svc.c \ 80*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_syscall.c \ 81*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_topology.c \ 82*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_pm.c \ 83*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_rng.c \ 84*f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/spmi_arb.c \ 85*f60617d3Squic_assethi $(QTI_PLAT_PATH)/qtiseclib/src/qtiseclib_cb_interface.c \ 86*f60617d3Squic_assethi 87*f60617d3Squic_assethi 88*f60617d3Squic_assethiPLAT_INCLUDES := -Iinclude/plat/common/ \ 89*f60617d3Squic_assethi ${QTI_EXTERNAL_INCLUDES} 90*f60617d3Squic_assethi 91*f60617d3Squic_assethiinclude lib/xlat_tables_v2/xlat_tables.mk 92*f60617d3Squic_assethiPLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \ 93*f60617d3Squic_assethi plat/common/aarch64/crash_console_helpers.S \ 94*f60617d3Squic_assethi common/desc_image_load.c \ 95*f60617d3Squic_assethi lib/bl_aux_params/bl_aux_params.c \ 96*f60617d3Squic_assethi 97*f60617d3Squic_assethiinclude lib/coreboot/coreboot.mk 98*f60617d3Squic_assethi 99*f60617d3Squic_assethi#PSCI Sources. 100*f60617d3Squic_assethiPSCI_SOURCES := plat/common/plat_psci_common.c \ 101*f60617d3Squic_assethi 102*f60617d3Squic_assethi# GIC-600 configuration 103*f60617d3Squic_assethiGICV3_SUPPORT_GIC600 := 1 104*f60617d3Squic_assethi# Include GICv3 driver files 105*f60617d3Squic_assethiinclude drivers/arm/gic/v3/gicv3.mk 106*f60617d3Squic_assethi 107*f60617d3Squic_assethi#Timer sources 108*f60617d3Squic_assethiTIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \ 109*f60617d3Squic_assethi drivers/delay_timer/delay_timer.c \ 110*f60617d3Squic_assethi 111*f60617d3Squic_assethi#GIC sources. 112*f60617d3Squic_assethiGIC_SOURCES := plat/common/plat_gicv3.c \ 113*f60617d3Squic_assethi ${GICV3_SOURCES} \ 114*f60617d3Squic_assethi 115*f60617d3Squic_assethiCPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \ 116*f60617d3Squic_assethi lib/cpus/aarch64/cortex_a55.S \ 117*f60617d3Squic_assethi 118*f60617d3Squic_assethiBL31_SOURCES += ${QTI_BL31_SOURCES} \ 119*f60617d3Squic_assethi ${PSCI_SOURCES} \ 120*f60617d3Squic_assethi ${GIC_SOURCES} \ 121*f60617d3Squic_assethi ${TIMER_SOURCES} \ 122*f60617d3Squic_assethi ${CPU_SOURCES} \ 123*f60617d3Squic_assethi 124*f60617d3Squic_assethiLIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET} 125*f60617d3Squic_assethi 126*f60617d3Squic_assethi 127*f60617d3Squic_assethi# Override this on the command line to point to the qtiseclib library which 128*f60617d3Squic_assethi# will be available in coreboot.org 129*f60617d3Squic_assethiQTISECLIB_PATH ?= 130*f60617d3Squic_assethi 131*f60617d3Squic_assethiifeq ($(QTISECLIB_PATH),) 132*f60617d3Squic_assethi# if No lib then use stub implementation for qtiseclib interface 133*f60617d3Squic_assethi$(warning QTISECLIB_PATH is not provided while building, using stub implementation. \ 134*f60617d3Squic_assethi Please refer docs/plat/qti.rst for more details \ 135*f60617d3Squic_assethi THIS FIRMWARE WILL NOT BOOT!) 136*f60617d3Squic_assethiBL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c 137*f60617d3Squic_assethielse 138*f60617d3Squic_assethi# use library provided by QTISECLIB_PATH 139*f60617d3Squic_assethiLDFLAGS += -L $(dir $(QTISECLIB_PATH)) 140*f60617d3Squic_assethiLDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH))) 141*f60617d3Squic_assethiendif 142*f60617d3Squic_assethi 143