1f60617d3Squic_assethi# 2d833129aSBoyan Karatotev# Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3f60617d3Squic_assethi# Copyright (c) 2024, The Linux Foundation. All rights reserved. 4f60617d3Squic_assethi# 5f60617d3Squic_assethi# SPDX-License-Identifier: BSD-3-Clause 6f60617d3Squic_assethi# 7f60617d3Squic_assethi 8f60617d3Squic_assethi# Makefile for QCS615 QTI platform. 9f60617d3Squic_assethi 10f60617d3Squic_assethiQTI_PLAT_PATH := plat/qti 11f60617d3Squic_assethiCHIPSET := ${PLAT} 12f60617d3Squic_assethi 13f60617d3Squic_assethi# Turn On Separate code & data. 14f60617d3Squic_assethiSEPARATE_CODE_AND_RODATA := 1 15f60617d3Squic_assethiUSE_COHERENT_MEM := 0 16f60617d3Squic_assethiWARMBOOT_ENABLE_DCACHE_EARLY := 1 17f60617d3Squic_assethiHW_ASSISTED_COHERENCY := 1 18f60617d3Squic_assethi 19f60617d3Squic_assethi# Enable errata configs for cortex_a76 and cortex_a55 20f60617d3Squic_assethi# QCS615 CPU core revisions are r1p0 21f60617d3Squic_assethiERRATA_A55_1221012 := 1 22f60617d3Squic_assethiERRATA_A55_1530923 := 1 23f60617d3Squic_assethiERRATA_A76_1073348 := 1 24f60617d3Squic_assethiERRATA_A76_1130799 := 1 25f60617d3Squic_assethiERRATA_A76_1220197 := 1 26f60617d3Squic_assethiERRATA_A76_1257314 := 1 27f60617d3Squic_assethiERRATA_A76_1262606 := 1 28f60617d3Squic_assethiERRATA_A76_1262888 := 1 29f60617d3Squic_assethiERRATA_A76_1275112 := 1 30f60617d3Squic_assethiERRATA_A76_1791580 := 1 31f60617d3Squic_assethiERRATA_A76_1165522 := 1 32f60617d3Squic_assethiERRATA_A76_1868343 := 1 33f60617d3Squic_assethiERRATA_A76_1946160 := 1 34f60617d3Squic_assethiERRATA_A76_2743102 := 1 35f60617d3Squic_assethi 36f60617d3Squic_assethi# Disable the PSCI platform compatibility layer 37f60617d3Squic_assethiENABLE_PLAT_COMPAT := 0 38f60617d3Squic_assethi 39f60617d3Squic_assethi# Enable PSCI v1.0 extended state ID format 40f60617d3Squic_assethiPSCI_EXTENDED_STATE_ID := 1 41f60617d3Squic_assethiARM_RECOM_STATE_ID_ENC := 1 42f60617d3Squic_assethiPSCI_OS_INIT_MODE := 1 43f60617d3Squic_assethi 44f60617d3Squic_assethiCOLD_BOOT_SINGLE_CPU := 1 45f60617d3Squic_assethiPROGRAMMABLE_RESET_ADDRESS := 1 46f60617d3Squic_assethi 47f60617d3Squic_assethiRESET_TO_BL31 := 0 48f60617d3Squic_assethi 497f86b635SSumit Garg# Enable the dynamic translation tables library 507f86b635SSumit GargPLAT_XLAT_TABLES_DYNAMIC := 1 517f86b635SSumit Garg$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) 527f86b635SSumit Garg 53f60617d3Squic_assethiQTI_SDI_BUILD := 0 54f60617d3Squic_assethi$(eval $(call assert_boolean,QTI_SDI_BUILD)) 55f60617d3Squic_assethi$(eval $(call add_define,QTI_SDI_BUILD)) 56f60617d3Squic_assethi 57f60617d3Squic_assethi#disable CTX_INCLUDE_AARCH32_REGS to support QCS615 gold cores 58f60617d3Squic_assethioverride CTX_INCLUDE_AARCH32_REGS := 0 59f60617d3Squic_assethi 60f60617d3Squic_assethi# Set dynamic CVE_2018_3639 explicitly as it defaults to 0. 61f60617d3Squic_assethi# Others which are applicable: CVE_2017_5715 & CVE_2022_23960 default to 1 62f60617d3Squic_assethiDYNAMIC_WORKAROUND_CVE_2018_3639 := 1 63f60617d3Squic_assethi 64f60617d3Squic_assethi# Enable stack protector. 65f60617d3Squic_assethiENABLE_STACK_PROTECTOR := strong 66f60617d3Squic_assethi 67f60617d3Squic_assethi 68f60617d3Squic_assethiQTI_EXTERNAL_INCLUDES := -I${QTI_PLAT_PATH}/${CHIPSET}/inc \ 69f60617d3Squic_assethi -I${QTI_PLAT_PATH}/common/inc \ 70f60617d3Squic_assethi -I${QTI_PLAT_PATH}/common/inc/$(ARCH) \ 71f60617d3Squic_assethi -I${QTI_PLAT_PATH}/qtiseclib/inc \ 72f60617d3Squic_assethi -I${QTI_PLAT_PATH}/qtiseclib/inc/${CHIPSET} \ 73f60617d3Squic_assethi 74f60617d3Squic_assethiQTI_BL31_SOURCES := $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_helpers.S \ 75f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_silver.S \ 76f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_gold.S \ 77f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_uart_console.S \ 78f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/pm_ps_hold.c \ 79f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_stack_protector.c \ 80f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_common.c \ 81f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_bl31_setup.c \ 82f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_gic_v3.c \ 83f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_interrupt_svc.c \ 84f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_syscall.c \ 85f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_topology.c \ 86f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/qti_pm.c \ 87f60617d3Squic_assethi $(QTI_PLAT_PATH)/common/src/spmi_arb.c \ 88f60617d3Squic_assethi $(QTI_PLAT_PATH)/qtiseclib/src/qtiseclib_cb_interface.c \ 89*1b9f8ec7SSumit Garg drivers/qti/crypto/rng.c 90f60617d3Squic_assethi 91f60617d3Squic_assethi 92f60617d3Squic_assethiPLAT_INCLUDES := -Iinclude/plat/common/ \ 93f60617d3Squic_assethi ${QTI_EXTERNAL_INCLUDES} 94f60617d3Squic_assethi 95f60617d3Squic_assethiinclude lib/xlat_tables_v2/xlat_tables.mk 96f60617d3Squic_assethiPLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \ 97f60617d3Squic_assethi plat/common/aarch64/crash_console_helpers.S \ 98f60617d3Squic_assethi common/desc_image_load.c \ 99f60617d3Squic_assethi lib/bl_aux_params/bl_aux_params.c \ 100f60617d3Squic_assethi 101f60617d3Squic_assethiinclude lib/coreboot/coreboot.mk 102f60617d3Squic_assethi 103f60617d3Squic_assethi#PSCI Sources. 104f60617d3Squic_assethiPSCI_SOURCES := plat/common/plat_psci_common.c \ 105f60617d3Squic_assethi 106f60617d3Squic_assethi# GIC-600 configuration 107f60617d3Squic_assethiGICV3_SUPPORT_GIC600 := 1 108f60617d3Squic_assethi# Include GICv3 driver files 109f60617d3Squic_assethiinclude drivers/arm/gic/v3/gicv3.mk 110f60617d3Squic_assethi 111f60617d3Squic_assethi#Timer sources 112f60617d3Squic_assethiTIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \ 113f60617d3Squic_assethi drivers/delay_timer/delay_timer.c \ 114f60617d3Squic_assethi 115f60617d3Squic_assethi#GIC sources. 116f60617d3Squic_assethiGIC_SOURCES := plat/common/plat_gicv3.c \ 117f60617d3Squic_assethi ${GICV3_SOURCES} \ 118f60617d3Squic_assethi 119f60617d3Squic_assethiCPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \ 120f60617d3Squic_assethi lib/cpus/aarch64/cortex_a55.S \ 121f60617d3Squic_assethi 122f60617d3Squic_assethiBL31_SOURCES += ${QTI_BL31_SOURCES} \ 123f60617d3Squic_assethi ${PSCI_SOURCES} \ 124f60617d3Squic_assethi ${GIC_SOURCES} \ 125f60617d3Squic_assethi ${TIMER_SOURCES} \ 126f60617d3Squic_assethi ${CPU_SOURCES} \ 127f60617d3Squic_assethi 128f60617d3Squic_assethiLIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET} 129f60617d3Squic_assethi 130f60617d3Squic_assethi 131f60617d3Squic_assethi# Override this on the command line to point to the qtiseclib library which 132f60617d3Squic_assethi# will be available in coreboot.org 133f60617d3Squic_assethiQTISECLIB_PATH ?= 134f60617d3Squic_assethi 135f60617d3Squic_assethiifeq ($(QTISECLIB_PATH),) 136f60617d3Squic_assethi# if No lib then use stub implementation for qtiseclib interface 137f60617d3Squic_assethi$(warning QTISECLIB_PATH is not provided while building, using stub implementation. \ 138f60617d3Squic_assethi Please refer docs/plat/qti.rst for more details \ 139f60617d3Squic_assethi THIS FIRMWARE WILL NOT BOOT!) 140f60617d3Squic_assethiBL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c 141f60617d3Squic_assethielse 142f60617d3Squic_assethi# use library provided by QTISECLIB_PATH 143d833129aSBoyan KaratotevLDLIBS += $(QTISECLIB_PATH) 144f60617d3Squic_assethiendif 145f60617d3Squic_assethi 146