1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2024, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 /* Enable the dynamic translation tables library. */ 12 #define PLAT_XLAT_TABLES_DYNAMIC 1 13 14 #include <common_def.h> 15 16 #include <qti_board_def.h> 17 #include <qtiseclib_defs_plat.h> 18 19 /*----------------------------------------------------------------------------*/ 20 21 /*----------------------------------------------------------------------------*/ 22 /* 23 * MPIDR_PRIMARY_CPU 24 * You just need to have the correct core_affinity_val i.e. [7:0] 25 * and cluster_affinity_val i.e. [15:8] 26 * the other bits will be ignored 27 */ 28 /*----------------------------------------------------------------------------*/ 29 #define MPIDR_PRIMARY_CPU 0x0000 30 /*----------------------------------------------------------------------------*/ 31 32 #define QTI_PWR_LVL0 MPIDR_AFFLVL0 33 #define QTI_PWR_LVL1 MPIDR_AFFLVL1 34 #define QTI_PWR_LVL2 MPIDR_AFFLVL2 35 #define QTI_PWR_LVL3 MPIDR_AFFLVL3 36 37 /* 38 * Macros for local power states encoded by State-ID field 39 * within the power-state parameter. 40 */ 41 /* Local power state for power domains in Run state. */ 42 #define QTI_LOCAL_STATE_RUN 0 43 /* 44 * Local power state for clock-gating. Valid only for CPU and not cluster power 45 * domains 46 */ 47 #define QTI_LOCAL_STATE_STB 1 48 /* 49 * Local power state for retention. Valid for CPU and cluster power 50 * domains 51 */ 52 #define QTI_LOCAL_STATE_RET 2 53 /* 54 * Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC 55 * power domains 56 */ 57 #define QTI_LOCAL_STATE_OFF 3 58 /* 59 * Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC 60 * power domains 61 */ 62 #define QTI_LOCAL_STATE_DEEPOFF 4 63 64 /* 65 * This macro defines the deepest retention state possible. A higher state 66 * id will represent an invalid or a power down state. 67 */ 68 #define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET 69 70 /* 71 * This macro defines the deepest power down states possible. Any state ID 72 * higher than this is invalid. 73 */ 74 #define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF 75 76 /****************************************************************************** 77 * Required platform porting definitions common to all ARM standard platforms 78 *****************************************************************************/ 79 80 /* 81 * Platform specific page table and MMU setup constants. 82 */ 83 #define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES) 84 85 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36) 86 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36) 87 88 #define ARM_CACHE_WRITEBACK_SHIFT 6 89 90 /* 91 * Some data must be aligned on the biggest cache line size in the platform. 92 * This is known only to the platform as it might have a combination of 93 * integrated and external caches. 94 */ 95 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 96 97 /* 98 * One cache line needed for bakery locks on ARM platforms 99 */ 100 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 101 102 /*----------------------------------------------------------------------------*/ 103 /* PSCI power domain topology definitions */ 104 /*----------------------------------------------------------------------------*/ 105 /* One domain each to represent RSC and PDC level */ 106 #define PLAT_PDC_COUNT 1 107 #define PLAT_RSC_COUNT 1 108 109 /* There is one top-level FCM cluster */ 110 #define PLAT_CLUSTER_COUNT 1 111 112 /* No. of cores in the FCM cluster */ 113 #define PLAT_CLUSTER0_CORE_COUNT 8 114 115 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT) 116 117 #define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\ 118 PLAT_RSC_COUNT +\ 119 PLAT_CLUSTER_COUNT +\ 120 PLATFORM_CORE_COUNT) 121 122 #define PLAT_MAX_PWR_LVL 3 123 124 /*****************************************************************************/ 125 /* Memory mapped Generic timer interfaces */ 126 /*****************************************************************************/ 127 128 /*----------------------------------------------------------------------------*/ 129 /* GIC-600 constants */ 130 /*----------------------------------------------------------------------------*/ 131 #define BASE_GICD_BASE 0x17A00000 132 #define BASE_GICR_BASE 0x17A60000 133 #define BASE_GICC_BASE 0x0 134 #define BASE_GICH_BASE 0x0 135 #define BASE_GICV_BASE 0x0 136 137 #define QTI_GICD_BASE BASE_GICD_BASE 138 #define QTI_GICR_BASE BASE_GICR_BASE 139 #define QTI_GICC_BASE BASE_GICC_BASE 140 141 /*----------------------------------------------------------------------------*/ 142 143 /*----------------------------------------------------------------------------*/ 144 /* UART related constants. */ 145 /*----------------------------------------------------------------------------*/ 146 /* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */ 147 #define GENI4_CFG 0x0 148 #define GENI4_IMAGE_REGS 0x100 149 #define GENI4_DATA 0x600 150 151 /* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */ 152 #define GENI_STATUS_REG (GENI4_CFG + 0x00000040) 153 #define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1) 154 #define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170) 155 /* MASTER/TX ENGINE REGISTERS */ 156 #define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000) 157 /* FIFO, STATUS REGISTERS AND MASKS */ 158 #define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100) 159 160 #define GENI_M_CMD_TX (0x08000000) 161 162 /*----------------------------------------------------------------------------*/ 163 /* Device address space for mapping. Excluding starting 4K */ 164 /*----------------------------------------------------------------------------*/ 165 #define QTI_DEVICE_BASE 0x1000 166 #define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE) 167 168 /******************************************************************************* 169 * BL31 specific defines. 170 ******************************************************************************/ 171 /* 172 * Put BL31 at DDR as per memory map. BL31_BASE is calculated using the 173 * current BL31 debug size plus a little space for growth. 174 */ 175 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 176 177 /*----------------------------------------------------------------------------*/ 178 /* AOSS registers */ 179 /*----------------------------------------------------------------------------*/ 180 #define QTI_PS_HOLD_REG 0x0C264000 181 /*----------------------------------------------------------------------------*/ 182 /* AOP CMD DB address space for mapping */ 183 /*----------------------------------------------------------------------------*/ 184 #define QTI_AOP_CMD_DB_BASE 0x85F20000 185 #define QTI_AOP_CMD_DB_SIZE 0x00020000 186 /*----------------------------------------------------------------------------*/ 187 /* SOC hw version register */ 188 /*----------------------------------------------------------------------------*/ 189 #define QTI_SOC_VERSION_MASK U(0xFFFF) 190 #define QTI_SOC_REVISION_REG 0x1FC8000 191 #define QTI_SOC_REVISION_MASK U(0xFFFF) 192 /*----------------------------------------------------------------------------*/ 193 /* LC PON register offsets */ 194 /*----------------------------------------------------------------------------*/ 195 #define PON_PS_HOLD_RESET_CTL 0x85a 196 #define PON_PS_HOLD_RESET_CTL2 0x85b 197 /*----------------------------------------------------------------------------*/ 198 199 #endif /* PLATFORM_DEF_H */ 200