1dddba19aSStephan Gerhold# 24a3e2cb3SStephan Gerhold# Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3dddba19aSStephan Gerhold# 4dddba19aSStephan Gerhold# SPDX-License-Identifier: BSD-3-Clause 5dddba19aSStephan Gerhold# 6dddba19aSStephan Gerhold 7dddba19aSStephan Gerholdinclude drivers/arm/gic/v2/gicv2.mk 8dddba19aSStephan Gerholdinclude lib/xlat_tables_v2/xlat_tables.mk 9dddba19aSStephan Gerhold 10840831b2SStephan GerholdPLAT_BL_COMMON_SOURCES := ${GICV2_SOURCES} \ 11840831b2SStephan Gerhold ${XLAT_TABLES_LIB_SRCS} \ 12840831b2SStephan Gerhold drivers/delay_timer/delay_timer.c \ 13840831b2SStephan Gerhold drivers/delay_timer/generic_delay_timer.c \ 14840831b2SStephan Gerhold plat/common/plat_gicv2.c \ 15840831b2SStephan Gerhold plat/qti/msm8916/msm8916_gicv2.c \ 16840831b2SStephan Gerhold plat/qti/msm8916/msm8916_setup.c \ 17840831b2SStephan Gerhold plat/qti/msm8916/${ARCH}/msm8916_helpers.S \ 18840831b2SStephan Gerhold plat/qti/msm8916/${ARCH}/uartdm_console.S 19840831b2SStephan Gerhold 20cf0a75f0SStephan GerholdMSM8916_CPU := $(if ${ARM_CORTEX_A7},cortex_a7,cortex_a53) 211240dc7eSStephan GerholdMSM8916_PM_SOURCES := drivers/arm/cci/cci.c \ 221240dc7eSStephan Gerhold lib/cpus/${ARCH}/${MSM8916_CPU}.S \ 23840831b2SStephan Gerhold plat/common/plat_psci_common.c \ 24840831b2SStephan Gerhold plat/qti/msm8916/msm8916_config.c \ 25840831b2SStephan Gerhold plat/qti/msm8916/msm8916_cpu_boot.c \ 26840831b2SStephan Gerhold plat/qti/msm8916/msm8916_pm.c \ 27840831b2SStephan Gerhold plat/qti/msm8916/msm8916_topology.c 28840831b2SStephan Gerhold 29840831b2SStephan GerholdBL31_SOURCES += ${MSM8916_PM_SOURCES} \ 30840831b2SStephan Gerhold plat/qti/msm8916/msm8916_bl31_setup.c 31dddba19aSStephan Gerhold 3245b2bd0aSStephan GerholdPLAT_INCLUDES := -Iplat/qti/msm8916/include 3345b2bd0aSStephan Gerhold 3445b2bd0aSStephan Gerholdifeq (${ARCH},aarch64) 3545b2bd0aSStephan Gerhold# arm_macros.S exists only on aarch64 currently 3645b2bd0aSStephan GerholdPLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} 3745b2bd0aSStephan Gerholdendif 38dddba19aSStephan Gerhold 39dddba19aSStephan Gerhold# Only BL31 is supported at the moment and is entered on a single CPU 40dddba19aSStephan GerholdRESET_TO_BL31 := 1 41dddba19aSStephan GerholdCOLD_BOOT_SINGLE_CPU := 1 42dddba19aSStephan Gerhold 43dddba19aSStephan Gerhold# Have different sections for code and rodata 44dddba19aSStephan GerholdSEPARATE_CODE_AND_RODATA := 1 45dddba19aSStephan Gerhold 46dddba19aSStephan Gerhold# Single cluster 47dddba19aSStephan GerholdWARMBOOT_ENABLE_DCACHE_EARLY := 1 48dddba19aSStephan Gerhold 49dddba19aSStephan Gerhold# Disable features unsupported in ARMv8.0 5090118bb5SAndre PrzywaraENABLE_SPE_FOR_NS := 0 51dddba19aSStephan GerholdENABLE_SVE_FOR_NS := 0 52dddba19aSStephan Gerhold 53cf0a75f0SStephan Gerhold# Disable workarounds unnecessary for Cortex-A7/A53 544a3e2cb3SStephan GerholdWORKAROUND_CVE_2017_5715 := 0 554a3e2cb3SStephan GerholdWORKAROUND_CVE_2022_23960 := 0 564a3e2cb3SStephan Gerhold 57cf0a75f0SStephan Gerholdifeq (${MSM8916_CPU},cortex_a53) 58c28e96cdSStephan Gerhold# The Cortex-A53 revision varies depending on the SoC revision. 59c28e96cdSStephan Gerhold# msm8916 uses r0p0, msm8939 uses r0p1 or r0p4. Enable all errata 60c28e96cdSStephan Gerhold# and rely on the runtime detection to apply them only if needed. 61dddba19aSStephan GerholdERRATA_A53_819472 := 1 62dddba19aSStephan GerholdERRATA_A53_824069 := 1 63dddba19aSStephan GerholdERRATA_A53_826319 := 1 64dddba19aSStephan GerholdERRATA_A53_827319 := 1 65dddba19aSStephan GerholdERRATA_A53_835769 := 1 66dddba19aSStephan GerholdERRATA_A53_836870 := 1 67dddba19aSStephan GerholdERRATA_A53_843419 := 1 68c28e96cdSStephan GerholdERRATA_A53_855873 := 1 69dddba19aSStephan GerholdERRATA_A53_1530924 := 1 70cf0a75f0SStephan Gerholdendif 71dddba19aSStephan Gerhold 724181ec8cSStephan Gerhold# Build config flags 734181ec8cSStephan Gerhold# ------------------ 744181ec8cSStephan GerholdBL31_BASE ?= 0x86500000 754181ec8cSStephan GerholdPRELOADED_BL33_BASE ?= 0x8f600000 764181ec8cSStephan Gerhold 7745b2bd0aSStephan Gerholdifeq (${ARCH},aarch64) 7845b2bd0aSStephan Gerhold BL32_BASE ?= BL31_LIMIT 79dddba19aSStephan Gerhold $(eval $(call add_define,BL31_BASE)) 8045b2bd0aSStephan Gerholdelse 81*043f38fdSJuan Pablo Conde ifeq (${AARCH32_SP},none) 82*043f38fdSJuan Pablo Conde $(error Variable AARCH32_SP has to be set for AArch32) 83*043f38fdSJuan Pablo Conde endif 8445b2bd0aSStephan Gerhold # There is no BL31 on aarch32, so reuse its location for BL32 8545b2bd0aSStephan Gerhold BL32_BASE ?= $(BL31_BASE) 8645b2bd0aSStephan Gerholdendif 87dddba19aSStephan Gerhold$(eval $(call add_define,BL32_BASE)) 88aad23f1aSStephan Gerhold 89aad23f1aSStephan Gerhold# UART number to use for TF-A output during early boot 90aad23f1aSStephan GerholdQTI_UART_NUM ?= 2 91aad23f1aSStephan Gerhold$(eval $(call assert_numeric,QTI_UART_NUM)) 92aad23f1aSStephan Gerhold$(eval $(call add_define,QTI_UART_NUM)) 93aad23f1aSStephan Gerhold 94aad23f1aSStephan Gerhold# Set to 1 on the command line to keep using UART after early boot. 95aad23f1aSStephan Gerhold# Requires reserving the UART and related clocks inside the normal world. 96aad23f1aSStephan GerholdQTI_RUNTIME_UART ?= 0 97aad23f1aSStephan Gerhold$(eval $(call assert_boolean,QTI_RUNTIME_UART)) 98aad23f1aSStephan Gerhold$(eval $(call add_define,QTI_RUNTIME_UART)) 99