1 /* 2 * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <drivers/arm/cci.h> 11 #include <lib/mmio.h> 12 13 #include "msm8916_config.h" 14 #include "msm8916_gicv2.h" 15 #include <msm8916_mmap.h> 16 #include <platform_def.h> 17 18 static const int cci_map[] = { 3, 4 }; 19 20 void msm8916_configure_early(void) 21 { 22 if (PLATFORM_CLUSTER_COUNT > 1) { 23 cci_init(APCS_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 24 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 25 } 26 } 27 28 static void msm8916_configure_timer(uintptr_t base) 29 { 30 /* Set timer frequency */ 31 mmio_write_32(base + CNTCTLBASE_CNTFRQ, PLAT_SYSCNT_FREQ); 32 33 /* Make all timer frames available to non-secure world */ 34 mmio_write_32(base + CNTNSAR, GENMASK_32(7, 0)); 35 } 36 37 /* 38 * The APCS register regions always start with a SECURE register that should 39 * be cleared to 0 to only allow secure access. Since BL31 handles most of 40 * the CPU power management, most of them can be cleared to secure access only. 41 */ 42 #define APCS_GLB_SECURE_STS_NS BIT_32(0) 43 #define APCS_GLB_SECURE_PWR_NS BIT_32(1) 44 #if PLATFORM_CORE_COUNT > 1 45 #define APCS_BOOT_START_ADDR_SEC 0x04 46 #define APCS_AA64NAA32_REG 0x0c 47 #else 48 #define APCS_BOOT_START_ADDR_SEC 0x18 49 #endif 50 #define REMAP_EN BIT_32(0) 51 52 static void msm8916_configure_apcs_cluster(unsigned int cluster) 53 { 54 uintptr_t cfg = APCS_CFG(cluster); 55 unsigned int cpu; 56 57 /* Disallow non-secure access to boot remapper / TCM registers */ 58 mmio_write_32(cfg, 0); 59 60 /* 61 * Disallow non-secure access to power management registers. 62 * However, allow STS and PWR since those also seem to control access 63 * to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these 64 * bits are not set, CPU frequency control fails in the non-secure world. 65 */ 66 mmio_write_32(APCS_GLB(cluster), 67 APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS); 68 69 if (PLATFORM_CORE_COUNT > 1) { 70 /* Disallow non-secure access to L2 SAW2 */ 71 mmio_write_32(APCS_L2_SAW2(cluster), 0); 72 73 /* Disallow non-secure access to CPU ACS and SAW2 */ 74 for (cpu = 0; cpu < PLATFORM_CPUS_PER_CLUSTER; cpu++) { 75 mmio_write_32(APCS_ALIAS_ACS(cluster, cpu), 0); 76 mmio_write_32(APCS_ALIAS_SAW2(cluster, cpu), 0); 77 } 78 } else { 79 /* There is just one core so no aliases exist */ 80 mmio_write_32(APCS_BANKED_ACS, 0); 81 mmio_write_32(APCS_BANKED_SAW2, 0); 82 } 83 84 #ifdef __aarch64__ 85 /* Make sure all further warm boots end up in BL31 and aarch64 state */ 86 CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned); 87 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN); 88 mmio_write_32(cfg + APCS_AA64NAA32_REG, 1); 89 #else 90 /* Make sure all further warm boots end up in BL32 */ 91 CASSERT((BL32_BASE & 0xffff) == 0, assert_bl32_base_64k_aligned); 92 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN); 93 #endif 94 95 msm8916_configure_timer(APCS_QTMR(cluster)); 96 } 97 98 static void msm8916_configure_apcs(void) 99 { 100 unsigned int cluster; 101 102 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; cluster++) { 103 msm8916_configure_apcs_cluster(cluster); 104 } 105 106 if (PLATFORM_CLUSTER_COUNT > 1) { 107 /* Disallow non-secure access to CCI ACS and SAW2 */ 108 mmio_write_32(APCS_CCI_ACS, 0); 109 mmio_write_32(APCS_CCI_SAW2, 0); 110 } 111 } 112 113 /* 114 * MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU, 115 * which allows routing context bank interrupts to one of 3 interrupt numbers 116 * ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number 117 * by default to avoid special setup on the non-secure side. 118 */ 119 #define CLK_OFF BIT_32(31) 120 #define GCC_APSS_TCU_CBCR (GCC_BASE + 0x12018) 121 #define GCC_GFX_TCU_CBCR (GCC_BASE + 0x12020) 122 #define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038) 123 #define GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x3600c) 124 #define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c) 125 #define APSS_TCU_CLK_ENA BIT_32(1) 126 #define GFX_TCU_CLK_ENA BIT_32(2) 127 #define GFX_TBU_CLK_ENA BIT_32(3) 128 #define SMMU_CFG_CLK_ENA BIT_32(12) 129 #define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000) 130 #define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff) 131 132 #define SMMU_SACR 0x010 133 #define SMMU_SACR_CACHE_LOCK BIT_32(26) 134 #define SMMU_IDR7 0x03c 135 #define SMMU_IDR7_MINOR(val) (((val) >> 0) & 0xf) 136 #define SMMU_IDR7_MAJOR(val) (((val) >> 4) & 0xf) 137 138 static void msm8916_smmu_cache_unlock(uintptr_t smmu_base, uintptr_t clk_cbcr) 139 { 140 uint32_t version; 141 142 /* Wait for clock */ 143 while (mmio_read_32(clk_cbcr) & CLK_OFF) { 144 } 145 146 version = mmio_read_32(smmu_base + SMMU_IDR7); 147 VERBOSE("SMMU(0x%lx) r%dp%d\n", smmu_base, 148 SMMU_IDR7_MAJOR(version), SMMU_IDR7_MINOR(version)); 149 150 /* For SMMU r2p0+ clear CACHE_LOCK to allow writes to CBn_ACTLR */ 151 if (SMMU_IDR7_MAJOR(version) >= 2) { 152 mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); 153 } 154 } 155 156 static void msm8916_configure_smmu(void) 157 { 158 uint32_t ena_bits = APSS_TCU_CLK_ENA | SMMU_CFG_CLK_ENA; 159 160 /* Single core (MDM) platforms do not have a GPU */ 161 if (PLATFORM_CORE_COUNT > 1) { 162 ena_bits |= GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA; 163 } 164 165 /* Enable SMMU clocks to enable register access */ 166 mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, ena_bits); 167 168 /* Wait for configuration clock */ 169 while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) { 170 } 171 172 /* Route all context bank interrupts to non-secure interrupt */ 173 mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL); 174 175 /* Clear sACR.CACHE_LOCK bit if needed for MMU-500 r2p0+ */ 176 msm8916_smmu_cache_unlock(APPS_SMMU_BASE, GCC_APSS_TCU_CBCR); 177 if (PLATFORM_CORE_COUNT > 1) { 178 msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR); 179 } 180 181 /* 182 * Keep APCS vote for SMMU clocks for rest of booting process, but make 183 * sure other vote registers (such as RPM) do not keep permanent votes. 184 */ 185 VERBOSE("Clearing GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (was: 0x%x)\n", 186 mmio_read_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE)); 187 mmio_write_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE, 0); 188 } 189 190 void msm8916_configure(void) 191 { 192 msm8916_gicv2_configure(); 193 msm8916_configure_apcs(); 194 msm8916_configure_smmu(); 195 } 196