1 /* 2 * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <lib/mmio.h> 11 12 #include "msm8916_config.h" 13 #include "msm8916_gicv2.h" 14 #include <msm8916_mmap.h> 15 #include <platform_def.h> 16 17 static void msm8916_configure_timer(uintptr_t base) 18 { 19 /* Set timer frequency */ 20 mmio_write_32(base + CNTCTLBASE_CNTFRQ, PLAT_SYSCNT_FREQ); 21 22 /* Make all timer frames available to non-secure world */ 23 mmio_write_32(base + CNTNSAR, GENMASK_32(7, 0)); 24 } 25 26 /* 27 * The APCS register regions always start with a SECURE register that should 28 * be cleared to 0 to only allow secure access. Since BL31 handles most of 29 * the CPU power management, most of them can be cleared to secure access only. 30 */ 31 #define APCS_GLB_SECURE_STS_NS BIT_32(0) 32 #define APCS_GLB_SECURE_PWR_NS BIT_32(1) 33 #define APCS_BOOT_START_ADDR_SEC 0x04 34 #define REMAP_EN BIT_32(0) 35 #define APCS_AA64NAA32_REG 0x0c 36 37 static void msm8916_configure_apcs_cluster(unsigned int cluster) 38 { 39 uintptr_t cfg = APCS_CFG(cluster); 40 unsigned int cpu; 41 42 /* Disallow non-secure access to boot remapper / TCM registers */ 43 mmio_write_32(cfg, 0); 44 45 /* 46 * Disallow non-secure access to power management registers. 47 * However, allow STS and PWR since those also seem to control access 48 * to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these 49 * bits are not set, CPU frequency control fails in the non-secure world. 50 */ 51 mmio_write_32(APCS_GLB(cluster), 52 APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS); 53 54 /* Disallow non-secure access to L2 SAW2 */ 55 mmio_write_32(APCS_L2_SAW2(cluster), 0); 56 57 /* Disallow non-secure access to CPU ACS and SAW2 */ 58 for (cpu = 0; cpu < PLATFORM_CPUS_PER_CLUSTER; cpu++) { 59 mmio_write_32(APCS_ALIAS_ACS(cluster, cpu), 0); 60 mmio_write_32(APCS_ALIAS_SAW2(cluster, cpu), 0); 61 } 62 63 #ifdef __aarch64__ 64 /* Make sure all further warm boots end up in BL31 and aarch64 state */ 65 CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned); 66 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN); 67 mmio_write_32(cfg + APCS_AA64NAA32_REG, 1); 68 #else 69 /* Make sure all further warm boots end up in BL32 */ 70 CASSERT((BL32_BASE & 0xffff) == 0, assert_bl32_base_64k_aligned); 71 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN); 72 #endif 73 74 msm8916_configure_timer(APCS_QTMR(cluster)); 75 } 76 77 static void msm8916_configure_apcs(void) 78 { 79 unsigned int cluster; 80 81 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; cluster++) { 82 msm8916_configure_apcs_cluster(cluster); 83 } 84 } 85 86 /* 87 * MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU, 88 * which allows routing context bank interrupts to one of 3 interrupt numbers 89 * ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number 90 * by default to avoid special setup on the non-secure side. 91 */ 92 #define CLK_OFF BIT_32(31) 93 #define GCC_APSS_TCU_CBCR (GCC_BASE + 0x12018) 94 #define GCC_GFX_TCU_CBCR (GCC_BASE + 0x12020) 95 #define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038) 96 #define GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x3600c) 97 #define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c) 98 #define APSS_TCU_CLK_ENA BIT_32(1) 99 #define GFX_TCU_CLK_ENA BIT_32(2) 100 #define GFX_TBU_CLK_ENA BIT_32(3) 101 #define SMMU_CFG_CLK_ENA BIT_32(12) 102 #define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000) 103 #define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff) 104 105 #define SMMU_SACR 0x010 106 #define SMMU_SACR_CACHE_LOCK BIT_32(26) 107 #define SMMU_IDR7 0x03c 108 #define SMMU_IDR7_MINOR(val) (((val) >> 0) & 0xf) 109 #define SMMU_IDR7_MAJOR(val) (((val) >> 4) & 0xf) 110 111 static void msm8916_smmu_cache_unlock(uintptr_t smmu_base, uintptr_t clk_cbcr) 112 { 113 uint32_t version; 114 115 /* Wait for clock */ 116 while (mmio_read_32(clk_cbcr) & CLK_OFF) { 117 } 118 119 version = mmio_read_32(smmu_base + SMMU_IDR7); 120 VERBOSE("SMMU(0x%lx) r%dp%d\n", smmu_base, 121 SMMU_IDR7_MAJOR(version), SMMU_IDR7_MINOR(version)); 122 123 /* For SMMU r2p0+ clear CACHE_LOCK to allow writes to CBn_ACTLR */ 124 if (SMMU_IDR7_MAJOR(version) >= 2) { 125 mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); 126 } 127 } 128 129 static void msm8916_configure_smmu(void) 130 { 131 /* Enable SMMU clocks to enable register access */ 132 mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA | 133 APSS_TCU_CLK_ENA | GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA); 134 135 /* Wait for configuration clock */ 136 while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) { 137 } 138 139 /* Route all context bank interrupts to non-secure interrupt */ 140 mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL); 141 142 /* Clear sACR.CACHE_LOCK bit if needed for MMU-500 r2p0+ */ 143 msm8916_smmu_cache_unlock(APPS_SMMU_BASE, GCC_APSS_TCU_CBCR); 144 msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR); 145 146 /* 147 * Keep APCS vote for SMMU clocks for rest of booting process, but make 148 * sure other vote registers (such as RPM) do not keep permanent votes. 149 */ 150 VERBOSE("Clearing GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (was: 0x%x)\n", 151 mmio_read_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE)); 152 mmio_write_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE, 0); 153 } 154 155 void msm8916_configure(void) 156 { 157 msm8916_gicv2_configure(); 158 msm8916_configure_apcs(); 159 msm8916_configure_smmu(); 160 } 161