1 /* 2 * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <drivers/arm/cci.h> 11 #include <lib/mmio.h> 12 13 #include "msm8916_config.h" 14 #include "msm8916_gicv2.h" 15 #include <msm8916_mmap.h> 16 #include <platform_def.h> 17 18 static const int cci_map[] = { 3, 4 }; 19 20 void msm8916_configure_early(void) 21 { 22 if (PLATFORM_CLUSTER_COUNT > 1) { 23 cci_init(APCS_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 24 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 25 } 26 } 27 28 static void msm8916_configure_timer(uintptr_t base) 29 { 30 /* Set timer frequency */ 31 mmio_write_32(base + CNTCTLBASE_CNTFRQ, PLAT_SYSCNT_FREQ); 32 33 /* Make all timer frames available to non-secure world */ 34 mmio_write_32(base + CNTNSAR, GENMASK_32(7, 0)); 35 } 36 37 /* 38 * The APCS register regions always start with a SECURE register that should 39 * be cleared to 0 to only allow secure access. Since BL31 handles most of 40 * the CPU power management, most of them can be cleared to secure access only. 41 */ 42 #define APCS_GLB_SECURE_STS_NS BIT_32(0) 43 #define APCS_GLB_SECURE_PWR_NS BIT_32(1) 44 #define APCS_BOOT_START_ADDR_SEC 0x04 45 #define REMAP_EN BIT_32(0) 46 #define APCS_AA64NAA32_REG 0x0c 47 48 static void msm8916_configure_apcs_cluster(unsigned int cluster) 49 { 50 uintptr_t cfg = APCS_CFG(cluster); 51 unsigned int cpu; 52 53 /* Disallow non-secure access to boot remapper / TCM registers */ 54 mmio_write_32(cfg, 0); 55 56 /* 57 * Disallow non-secure access to power management registers. 58 * However, allow STS and PWR since those also seem to control access 59 * to CPU frequency related registers (e.g. APCS_CMD_RCGR). If these 60 * bits are not set, CPU frequency control fails in the non-secure world. 61 */ 62 mmio_write_32(APCS_GLB(cluster), 63 APCS_GLB_SECURE_STS_NS | APCS_GLB_SECURE_PWR_NS); 64 65 /* Disallow non-secure access to L2 SAW2 */ 66 mmio_write_32(APCS_L2_SAW2(cluster), 0); 67 68 /* Disallow non-secure access to CPU ACS and SAW2 */ 69 for (cpu = 0; cpu < PLATFORM_CPUS_PER_CLUSTER; cpu++) { 70 mmio_write_32(APCS_ALIAS_ACS(cluster, cpu), 0); 71 mmio_write_32(APCS_ALIAS_SAW2(cluster, cpu), 0); 72 } 73 74 #ifdef __aarch64__ 75 /* Make sure all further warm boots end up in BL31 and aarch64 state */ 76 CASSERT((BL31_BASE & 0xffff) == 0, assert_bl31_base_64k_aligned); 77 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL31_BASE | REMAP_EN); 78 mmio_write_32(cfg + APCS_AA64NAA32_REG, 1); 79 #else 80 /* Make sure all further warm boots end up in BL32 */ 81 CASSERT((BL32_BASE & 0xffff) == 0, assert_bl32_base_64k_aligned); 82 mmio_write_32(cfg + APCS_BOOT_START_ADDR_SEC, BL32_BASE | REMAP_EN); 83 #endif 84 85 msm8916_configure_timer(APCS_QTMR(cluster)); 86 } 87 88 static void msm8916_configure_apcs(void) 89 { 90 unsigned int cluster; 91 92 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; cluster++) { 93 msm8916_configure_apcs_cluster(cluster); 94 } 95 96 if (PLATFORM_CLUSTER_COUNT > 1) { 97 /* Disallow non-secure access to CCI ACS and SAW2 */ 98 mmio_write_32(APCS_CCI_ACS, 0); 99 mmio_write_32(APCS_CCI_SAW2, 0); 100 } 101 } 102 103 /* 104 * MSM8916 has a special "interrupt aggregation logic" in the APPS SMMU, 105 * which allows routing context bank interrupts to one of 3 interrupt numbers 106 * ("TZ/HYP/NS"). Route all interrupts to the non-secure interrupt number 107 * by default to avoid special setup on the non-secure side. 108 */ 109 #define CLK_OFF BIT_32(31) 110 #define GCC_APSS_TCU_CBCR (GCC_BASE + 0x12018) 111 #define GCC_GFX_TCU_CBCR (GCC_BASE + 0x12020) 112 #define GCC_SMMU_CFG_CBCR (GCC_BASE + 0x12038) 113 #define GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x3600c) 114 #define GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE (GCC_BASE + 0x4500c) 115 #define APSS_TCU_CLK_ENA BIT_32(1) 116 #define GFX_TCU_CLK_ENA BIT_32(2) 117 #define GFX_TBU_CLK_ENA BIT_32(3) 118 #define SMMU_CFG_CLK_ENA BIT_32(12) 119 #define APPS_SMMU_INTR_SEL_NS (APPS_SMMU_QCOM + 0x2000) 120 #define APPS_SMMU_INTR_SEL_NS_EN_ALL U(0xffffffff) 121 122 #define SMMU_SACR 0x010 123 #define SMMU_SACR_CACHE_LOCK BIT_32(26) 124 #define SMMU_IDR7 0x03c 125 #define SMMU_IDR7_MINOR(val) (((val) >> 0) & 0xf) 126 #define SMMU_IDR7_MAJOR(val) (((val) >> 4) & 0xf) 127 128 static void msm8916_smmu_cache_unlock(uintptr_t smmu_base, uintptr_t clk_cbcr) 129 { 130 uint32_t version; 131 132 /* Wait for clock */ 133 while (mmio_read_32(clk_cbcr) & CLK_OFF) { 134 } 135 136 version = mmio_read_32(smmu_base + SMMU_IDR7); 137 VERBOSE("SMMU(0x%lx) r%dp%d\n", smmu_base, 138 SMMU_IDR7_MAJOR(version), SMMU_IDR7_MINOR(version)); 139 140 /* For SMMU r2p0+ clear CACHE_LOCK to allow writes to CBn_ACTLR */ 141 if (SMMU_IDR7_MAJOR(version) >= 2) { 142 mmio_clrbits_32(smmu_base + SMMU_SACR, SMMU_SACR_CACHE_LOCK); 143 } 144 } 145 146 static void msm8916_configure_smmu(void) 147 { 148 /* Enable SMMU clocks to enable register access */ 149 mmio_write_32(GCC_APCS_SMMU_CLOCK_BRANCH_ENA_VOTE, SMMU_CFG_CLK_ENA | 150 APSS_TCU_CLK_ENA | GFX_TCU_CLK_ENA | GFX_TBU_CLK_ENA); 151 152 /* Wait for configuration clock */ 153 while (mmio_read_32(GCC_SMMU_CFG_CBCR) & CLK_OFF) { 154 } 155 156 /* Route all context bank interrupts to non-secure interrupt */ 157 mmio_write_32(APPS_SMMU_INTR_SEL_NS, APPS_SMMU_INTR_SEL_NS_EN_ALL); 158 159 /* Clear sACR.CACHE_LOCK bit if needed for MMU-500 r2p0+ */ 160 msm8916_smmu_cache_unlock(APPS_SMMU_BASE, GCC_APSS_TCU_CBCR); 161 msm8916_smmu_cache_unlock(GPU_SMMU_BASE, GCC_GFX_TCU_CBCR); 162 163 /* 164 * Keep APCS vote for SMMU clocks for rest of booting process, but make 165 * sure other vote registers (such as RPM) do not keep permanent votes. 166 */ 167 VERBOSE("Clearing GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE (was: 0x%x)\n", 168 mmio_read_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE)); 169 mmio_write_32(GCC_RPM_SMMU_CLOCK_BRANCH_ENA_VOTE, 0); 170 } 171 172 void msm8916_configure(void) 173 { 174 msm8916_gicv2_configure(); 175 msm8916_configure_apcs(); 176 msm8916_configure_smmu(); 177 } 178