1*5bd9c17dSSaurabh Gorecha /* 2*5bd9c17dSSaurabh Gorecha * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*5bd9c17dSSaurabh Gorecha * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved. 4*5bd9c17dSSaurabh Gorecha * 5*5bd9c17dSSaurabh Gorecha * SPDX-License-Identifier: BSD-3-Clause 6*5bd9c17dSSaurabh Gorecha */ 7*5bd9c17dSSaurabh Gorecha #include <assert.h> 8*5bd9c17dSSaurabh Gorecha #include <stdint.h> 9*5bd9c17dSSaurabh Gorecha 10*5bd9c17dSSaurabh Gorecha #include <arch_helpers.h> 11*5bd9c17dSSaurabh Gorecha #include <bl31/interrupt_mgmt.h> 12*5bd9c17dSSaurabh Gorecha #include <drivers/arm/gic_common.h> 13*5bd9c17dSSaurabh Gorecha #include <lib/el3_runtime/context_mgmt.h> 14*5bd9c17dSSaurabh Gorecha 15*5bd9c17dSSaurabh Gorecha #include <platform.h> 16*5bd9c17dSSaurabh Gorecha #include <qti_interrupt_svc.h> 17*5bd9c17dSSaurabh Gorecha #include <qtiseclib_interface.h> 18*5bd9c17dSSaurabh Gorecha 19*5bd9c17dSSaurabh Gorecha #define QTI_INTR_INVALID_INT_NUM 0xFFFFFFFFU 20*5bd9c17dSSaurabh Gorecha 21*5bd9c17dSSaurabh Gorecha /* 22*5bd9c17dSSaurabh Gorecha * Top-level EL3 interrupt handler. 23*5bd9c17dSSaurabh Gorecha */ 24*5bd9c17dSSaurabh Gorecha static uint64_t qti_el3_interrupt_handler(uint32_t id, uint32_t flags, 25*5bd9c17dSSaurabh Gorecha void *handle, void *cookie) 26*5bd9c17dSSaurabh Gorecha { 27*5bd9c17dSSaurabh Gorecha uint32_t irq = QTI_INTR_INVALID_INT_NUM; 28*5bd9c17dSSaurabh Gorecha 29*5bd9c17dSSaurabh Gorecha /* 30*5bd9c17dSSaurabh Gorecha * EL3 non-interruptible. Interrupt shouldn't occur when we are at 31*5bd9c17dSSaurabh Gorecha * EL3 / Secure. 32*5bd9c17dSSaurabh Gorecha */ 33*5bd9c17dSSaurabh Gorecha assert(handle != cm_get_context(SECURE)); 34*5bd9c17dSSaurabh Gorecha 35*5bd9c17dSSaurabh Gorecha irq = plat_ic_acknowledge_interrupt(); 36*5bd9c17dSSaurabh Gorecha 37*5bd9c17dSSaurabh Gorecha qtiseclib_invoke_isr(irq, handle); 38*5bd9c17dSSaurabh Gorecha 39*5bd9c17dSSaurabh Gorecha /* End of Interrupt. */ 40*5bd9c17dSSaurabh Gorecha if (irq < 1022U) { 41*5bd9c17dSSaurabh Gorecha plat_ic_end_of_interrupt(irq); 42*5bd9c17dSSaurabh Gorecha } 43*5bd9c17dSSaurabh Gorecha 44*5bd9c17dSSaurabh Gorecha return (uint64_t) handle; 45*5bd9c17dSSaurabh Gorecha } 46*5bd9c17dSSaurabh Gorecha 47*5bd9c17dSSaurabh Gorecha int qti_interrupt_svc_init(void) 48*5bd9c17dSSaurabh Gorecha { 49*5bd9c17dSSaurabh Gorecha int ret; 50*5bd9c17dSSaurabh Gorecha uint64_t flags = 0U; 51*5bd9c17dSSaurabh Gorecha 52*5bd9c17dSSaurabh Gorecha /* 53*5bd9c17dSSaurabh Gorecha * Route EL3 interrupts to EL3 when in Non-secure. 54*5bd9c17dSSaurabh Gorecha * Note: EL3 won't have interrupt enable 55*5bd9c17dSSaurabh Gorecha * & we don't have S-EL1 support. 56*5bd9c17dSSaurabh Gorecha */ 57*5bd9c17dSSaurabh Gorecha set_interrupt_rm_flag(flags, NON_SECURE); 58*5bd9c17dSSaurabh Gorecha 59*5bd9c17dSSaurabh Gorecha /* Register handler for EL3 interrupts */ 60*5bd9c17dSSaurabh Gorecha ret = register_interrupt_type_handler(INTR_TYPE_EL3, 61*5bd9c17dSSaurabh Gorecha qti_el3_interrupt_handler, flags); 62*5bd9c17dSSaurabh Gorecha assert(ret == 0); 63*5bd9c17dSSaurabh Gorecha 64*5bd9c17dSSaurabh Gorecha return ret; 65*5bd9c17dSSaurabh Gorecha } 66