1 /* 2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2024, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <common/bl_common.h> 9 #include <drivers/arm/gicv3.h> 10 11 #include <platform.h> 12 #include <platform_def.h> 13 #include <qti_plat.h> 14 #include <qtiseclib_defs.h> 15 #include <qtiseclib_defs_plat.h> 16 17 /* The GICv3 driver only needs to be initialized in EL3 */ 18 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 19 20 /* Array of interrupts to be configured by the gic driver */ 21 static const interrupt_prop_t qti_interrupt_props[] = { 22 INTR_PROP_DESC(QTISECLIB_INT_ID_CPU_WAKEUP_SGI, 23 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 24 GIC_INTR_CFG_EDGE), 25 INTR_PROP_DESC(QTISECLIB_INT_ID_RESET_SGI, GIC_HIGHEST_SEC_PRIORITY, 26 INTR_GROUP0, 27 GIC_INTR_CFG_EDGE), 28 INTR_PROP_DESC(QTISECLIB_INT_ID_SEC_WDOG_BARK, GIC_HIGHEST_SEC_PRIORITY, 29 INTR_GROUP0, 30 GIC_INTR_CFG_EDGE), 31 INTR_PROP_DESC(QTISECLIB_INT_ID_NON_SEC_WDOG_BITE, 32 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 33 GIC_INTR_CFG_LEVEL), 34 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC, 35 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 36 GIC_INTR_CFG_EDGE), 37 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC, 38 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 39 GIC_INTR_CFG_EDGE), 40 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC, 41 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 42 GIC_INTR_CFG_EDGE), 43 INTR_PROP_DESC(QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC, 44 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 45 GIC_INTR_CFG_EDGE), 46 INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_SEC, GIC_HIGHEST_SEC_PRIORITY, 47 INTR_GROUP0, 48 GIC_INTR_CFG_EDGE), 49 INTR_PROP_DESC(QTISECLIB_INT_ID_XPU_NON_SEC, GIC_HIGHEST_SEC_PRIORITY, 50 INTR_GROUP0, 51 GIC_INTR_CFG_EDGE), 52 #ifdef QTISECLIB_INT_ID_A1_NOC_ERROR 53 INTR_PROP_DESC(QTISECLIB_INT_ID_A1_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY, 54 INTR_GROUP0, 55 GIC_INTR_CFG_EDGE), 56 #endif 57 #ifdef QTISECLIB_INT_ID_A2_NOC_ERROR 58 INTR_PROP_DESC(QTISECLIB_INT_ID_A2_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY, 59 INTR_GROUP0, 60 GIC_INTR_CFG_EDGE), 61 #endif 62 #ifdef QTISECLIB_INT_ID_CONFIG_NOC_ERROR 63 INTR_PROP_DESC(QTISECLIB_INT_ID_CONFIG_NOC_ERROR, 64 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 65 GIC_INTR_CFG_EDGE), 66 #endif 67 #ifdef QTISECLIB_INT_ID_DC_NOC_ERROR 68 INTR_PROP_DESC(QTISECLIB_INT_ID_DC_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY, 69 INTR_GROUP0, 70 GIC_INTR_CFG_EDGE), 71 #endif 72 #ifdef QTISECLIB_INT_ID_MEM_NOC_ERROR 73 INTR_PROP_DESC(QTISECLIB_INT_ID_MEM_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY, 74 INTR_GROUP0, 75 GIC_INTR_CFG_EDGE), 76 #endif 77 #ifdef QTISECLIB_INT_ID_SYSTEM_NOC_ERROR 78 INTR_PROP_DESC(QTISECLIB_INT_ID_SYSTEM_NOC_ERROR, 79 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 80 GIC_INTR_CFG_EDGE), 81 #endif 82 #ifdef QTISECLIB_INT_ID_MMSS_NOC_ERROR 83 INTR_PROP_DESC(QTISECLIB_INT_ID_MMSS_NOC_ERROR, 84 GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0, 85 GIC_INTR_CFG_EDGE), 86 #endif 87 #ifdef QTISECLIB_INT_ID_LPASS_AGNOC_ERROR 88 INTR_PROP_DESC(QTISECLIB_INT_ID_LPASS_AGNOC_ERROR, GIC_HIGHEST_SEC_PRIORITY, 89 INTR_GROUP0, 90 GIC_INTR_CFG_EDGE), 91 #endif 92 #ifdef QTISECLIB_INT_ID_NSP_NOC_ERROR 93 INTR_PROP_DESC(QTISECLIB_INT_ID_NSP_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY, 94 INTR_GROUP0, 95 GIC_INTR_CFG_EDGE), 96 #endif 97 }; 98 99 const gicv3_driver_data_t qti_gic_data = { 100 .gicd_base = QTI_GICD_BASE, 101 .gicr_base = QTI_GICR_BASE, 102 .interrupt_props = qti_interrupt_props, 103 .interrupt_props_num = ARRAY_SIZE(qti_interrupt_props), 104 .rdistif_num = PLATFORM_CORE_COUNT, 105 .rdistif_base_addrs = rdistif_base_addrs, 106 .mpidr_to_core_pos = plat_qti_core_pos_by_mpidr 107 }; 108 109 void plat_qti_gic_driver_init(void) 110 { 111 /* 112 * The GICv3 driver is initialized in EL3 and does not need 113 * to be initialized again in SEL1. This is because the S-EL1 114 * can use GIC system registers to manage interrupts and does 115 * not need GIC interface base addresses to be configured. 116 */ 117 gicv3_driver_init(&qti_gic_data); 118 } 119 120 /****************************************************************************** 121 * ARM common helper to initialize the GIC. Only invoked by BL31 122 *****************************************************************************/ 123 void plat_qti_gic_init(void) 124 { 125 unsigned int i; 126 127 gicv3_distif_init(); 128 gicv3_rdistif_init(plat_my_core_pos()); 129 gicv3_cpuif_enable(plat_my_core_pos()); 130 131 /* Route secure spi interrupt to ANY. */ 132 for (i = 0; i < ARRAY_SIZE(qti_interrupt_props); i++) { 133 unsigned int int_id = qti_interrupt_props[i].intr_num; 134 135 if (plat_ic_is_spi(int_id)) { 136 gicv3_set_spi_routing(int_id, GICV3_IRM_ANY, 0x0); 137 } 138 } 139 } 140 141 void gic_set_spi_routing(unsigned int id, unsigned int irm, u_register_t target) 142 { 143 gicv3_set_spi_routing(id, irm, target); 144 } 145 146 /****************************************************************************** 147 * ARM common helper to enable the GIC CPU interface 148 *****************************************************************************/ 149 void plat_qti_gic_cpuif_enable(void) 150 { 151 gicv3_cpuif_enable(plat_my_core_pos()); 152 } 153 154 /****************************************************************************** 155 * ARM common helper to disable the GIC CPU interface 156 *****************************************************************************/ 157 void plat_qti_gic_cpuif_disable(void) 158 { 159 gicv3_cpuif_disable(plat_my_core_pos()); 160 } 161 162 /****************************************************************************** 163 * ARM common helper to initialize the per-CPU redistributor interface in GICv3 164 *****************************************************************************/ 165 void plat_qti_gic_pcpu_init(void) 166 { 167 gicv3_rdistif_init(plat_my_core_pos()); 168 } 169 170 /****************************************************************************** 171 * ARM common helpers to power GIC redistributor interface 172 *****************************************************************************/ 173 void plat_qti_gic_redistif_on(void) 174 { 175 gicv3_rdistif_on(plat_my_core_pos()); 176 } 177 178 void plat_qti_gic_redistif_off(void) 179 { 180 gicv3_rdistif_off(plat_my_core_pos()); 181 } 182