1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include <common/debug.h> 14 #include <lib/mmio.h> 15 #include <lib/smccc.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <services/arm_arch_svc.h> 18 19 #include <platform_def.h> 20 #include <qti_map_chipinfo.h> 21 #include <qti_plat.h> 22 #include <qtiseclib_interface.h> 23 24 /* 25 * Table of regions for various BL stages to map using the MMU. 26 * This doesn't include TZRAM as the 'mem_layout' argument passed to 27 * qti_configure_mmu_elx() will give the available subset of that, 28 */ 29 30 const mmap_region_t plat_qti_mmap[] = { 31 MAP_REGION_FLAT(QTI_DEVICE_BASE, QTI_DEVICE_SIZE, 32 MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(QTI_AOP_CMD_DB_BASE, QTI_AOP_CMD_DB_SIZE, 34 MT_NS | MT_RO | MT_EXECUTE_NEVER), 35 {0} 36 }; 37 38 CASSERT(ARRAY_SIZE(plat_qti_mmap) <= MAX_MMAP_REGIONS, assert_max_mmap_regions); 39 40 41 bool qti_is_overlap_atf_rg(unsigned long long addr, size_t size) 42 { 43 if (addr > addr + size 44 || (BL31_BASE < addr + size && BL31_LIMIT > addr)) { 45 return true; 46 } 47 return false; 48 } 49 50 /* 51 * unsigned int plat_qti_my_cluster_pos(void) 52 * definition to get the cluster index of the calling CPU. 53 * - In ARM v8 (MPIDR_EL1[24]=0) 54 * ClusterId = MPIDR_EL1[15:8] 55 * - In ARM v8.1 & Later version (MPIDR_EL1[24]=1) 56 * ClusterId = MPIDR_EL1[23:15] 57 */ 58 unsigned int plat_qti_my_cluster_pos(void) 59 { 60 unsigned int mpidr, cluster_id; 61 62 mpidr = read_mpidr_el1(); 63 if ((mpidr & MPIDR_MT_MASK) == 0) { /* MT not supported */ 64 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 65 } else { /* MT supported */ 66 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; 67 } 68 assert(cluster_id < PLAT_CLUSTER_COUNT); 69 return cluster_id; 70 } 71 72 /* 73 * Set up the page tables for the generic and platform-specific memory regions. 74 * The extents of the generic memory regions are specified by the function 75 * arguments and consist of: 76 * - Trusted SRAM seen by the BL image; 77 * - Code section; 78 * - Read-only data section; 79 * - Coherent memory region, if applicable. 80 */ 81 void qti_setup_page_tables( 82 uintptr_t total_base, 83 size_t total_size, 84 uintptr_t code_start, 85 uintptr_t code_limit, 86 uintptr_t rodata_start, 87 uintptr_t rodata_limit 88 ) 89 { 90 /* 91 * Map the Trusted SRAM with appropriate memory attributes. 92 * Subsequent mappings will adjust the attributes for specific regions. 93 */ 94 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", 95 (void *)total_base, (void *)(total_base + total_size)); 96 mmap_add_region(total_base, total_base, 97 total_size, MT_MEMORY | MT_RW | MT_SECURE); 98 99 /* Re-map the code section */ 100 VERBOSE("Code region: %p - %p\n", 101 (void *)code_start, (void *)code_limit); 102 mmap_add_region(code_start, code_start, 103 code_limit - code_start, MT_CODE | MT_SECURE); 104 105 /* Re-map the read-only data section */ 106 VERBOSE("Read-only data region: %p - %p\n", 107 (void *)rodata_start, (void *)rodata_limit); 108 mmap_add_region(rodata_start, rodata_start, 109 rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE); 110 111 /* Now (re-)map the platform-specific memory regions */ 112 mmap_add(plat_qti_mmap); 113 114 /* Create the page tables to reflect the above mappings */ 115 init_xlat_tables(); 116 } 117 118 static inline void qti_align_mem_region(uintptr_t addr, size_t size, 119 uintptr_t *aligned_addr, 120 size_t *aligned_size) 121 { 122 *aligned_addr = round_down(addr, PAGE_SIZE); 123 *aligned_size = round_up(addr - *aligned_addr + size, PAGE_SIZE); 124 } 125 126 int qti_mmap_add_dynamic_region(uintptr_t base_pa, size_t size, 127 unsigned int attr) 128 { 129 uintptr_t aligned_pa; 130 size_t aligned_size; 131 132 qti_align_mem_region(base_pa, size, &aligned_pa, &aligned_size); 133 134 if (qti_is_overlap_atf_rg(base_pa, size)) { 135 /* Memory shouldn't overlap with TF-A range. */ 136 return -EPERM; 137 } 138 139 return mmap_add_dynamic_region(aligned_pa, aligned_pa, aligned_size, 140 attr); 141 } 142 143 int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size) 144 { 145 qti_align_mem_region(base_va, size, &base_va, &size); 146 return mmap_remove_dynamic_region(base_va, size); 147 } 148 149 /* 150 * This function returns soc version which mainly consist of below fields 151 * 152 * soc_version[30:24] = JEP-106 continuation code for the SiP 153 * soc_version[23:16] = JEP-106 identification code with parity bit for the SiP 154 * soc_version[0:15] = Implementation defined SoC ID 155 */ 156 int32_t plat_get_soc_version(void) 157 { 158 int i = 0; 159 /* Variant other than in mapped g_map_jtag_chipinfo_id variable will have 160 * default chipinfo id as 0xFFFF 161 */ 162 uint32_t soc_version = (QTI_DEFAULT_CHIPINFO_ID & QTI_SOC_VERSION_MASK); 163 uint32_t jep106az_code = (JEDEC_QTI_BKID << QTI_SOC_CONTINUATION_SHIFT) 164 | (JEDEC_QTI_MFID << QTI_SOC_IDENTIFICATION_SHIFT); 165 uint32_t jtag_id = mmio_read_32(QTI_JTAG_ID_REG); 166 uint32_t jtag_id_val = (jtag_id >> QTI_JTAG_ID_SHIFT) 167 & QTI_SOC_VERSION_MASK; 168 169 for (i = 0; i < ARRAY_SIZE(g_map_jtag_chipinfo_id); i++) { 170 if (g_map_jtag_chipinfo_id[i].jtag_id == jtag_id_val) 171 soc_version = g_map_jtag_chipinfo_id[i].chipinfo_id 172 & QTI_SOC_VERSION_MASK; 173 } 174 return (int32_t)(jep106az_code | (soc_version)); 175 } 176 177 /* 178 * This function returns soc revision in below format 179 * 180 * soc_revision[0:30] = SOC revision of specific SOC 181 */ 182 int32_t plat_get_soc_revision(void) 183 { 184 return mmio_read_32(QTI_SOC_REVISION_REG) & QTI_SOC_REVISION_MASK; 185 } 186 187 /***************************************************************************** 188 * plat_is_smccc_feature_available() - This function checks whether SMCCC feature 189 * is availabile for the platform or not. 190 * @fid: SMCCC function id 191 * 192 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 193 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 194 *****************************************************************************/ 195 int32_t plat_is_smccc_feature_available(u_register_t fid) 196 { 197 switch (fid) { 198 case SMCCC_ARCH_SOC_ID: 199 return SMC_ARCH_CALL_SUCCESS; 200 default: 201 return SMC_ARCH_CALL_NOT_SUPPORTED; 202 } 203 } 204