xref: /rk3399_ARM-atf/plat/qti/common/src/qti_common.c (revision 5bd9c17d023288e6b819fa3eecc01b7981399cfa)
1*5bd9c17dSSaurabh Gorecha /*
2*5bd9c17dSSaurabh Gorecha  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*5bd9c17dSSaurabh Gorecha  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4*5bd9c17dSSaurabh Gorecha  *
5*5bd9c17dSSaurabh Gorecha  * SPDX-License-Identifier: BSD-3-Clause
6*5bd9c17dSSaurabh Gorecha  */
7*5bd9c17dSSaurabh Gorecha 
8*5bd9c17dSSaurabh Gorecha #include <assert.h>
9*5bd9c17dSSaurabh Gorecha #include <errno.h>
10*5bd9c17dSSaurabh Gorecha #include <stdbool.h>
11*5bd9c17dSSaurabh Gorecha #include <stdint.h>
12*5bd9c17dSSaurabh Gorecha 
13*5bd9c17dSSaurabh Gorecha #include <common/debug.h>
14*5bd9c17dSSaurabh Gorecha #include <lib/xlat_tables/xlat_tables_v2.h>
15*5bd9c17dSSaurabh Gorecha 
16*5bd9c17dSSaurabh Gorecha #include <platform_def.h>
17*5bd9c17dSSaurabh Gorecha #include <qti_plat.h>
18*5bd9c17dSSaurabh Gorecha #include <qtiseclib_interface.h>
19*5bd9c17dSSaurabh Gorecha 
20*5bd9c17dSSaurabh Gorecha /*
21*5bd9c17dSSaurabh Gorecha  * Table of regions for various BL stages to map using the MMU.
22*5bd9c17dSSaurabh Gorecha  * This doesn't include TZRAM as the 'mem_layout' argument passed to
23*5bd9c17dSSaurabh Gorecha  * qti_configure_mmu_elx() will give the available subset of that,
24*5bd9c17dSSaurabh Gorecha  */
25*5bd9c17dSSaurabh Gorecha 
26*5bd9c17dSSaurabh Gorecha const mmap_region_t plat_qti_mmap[] = {
27*5bd9c17dSSaurabh Gorecha 	MAP_REGION_FLAT(QTI_DEVICE_BASE, QTI_DEVICE_SIZE,
28*5bd9c17dSSaurabh Gorecha 			MT_DEVICE | MT_RW | MT_SECURE),
29*5bd9c17dSSaurabh Gorecha 	MAP_REGION_FLAT(QTI_AOP_CMD_DB_BASE, QTI_AOP_CMD_DB_SIZE,
30*5bd9c17dSSaurabh Gorecha 			MT_NS | MT_RO | MT_EXECUTE_NEVER),
31*5bd9c17dSSaurabh Gorecha 	{0}
32*5bd9c17dSSaurabh Gorecha };
33*5bd9c17dSSaurabh Gorecha 
34*5bd9c17dSSaurabh Gorecha CASSERT(ARRAY_SIZE(plat_qti_mmap) <= MAX_MMAP_REGIONS, assert_max_mmap_regions);
35*5bd9c17dSSaurabh Gorecha 
36*5bd9c17dSSaurabh Gorecha 
37*5bd9c17dSSaurabh Gorecha bool qti_is_overlap_atf_rg(unsigned long long addr, size_t size)
38*5bd9c17dSSaurabh Gorecha {
39*5bd9c17dSSaurabh Gorecha 	if (addr > addr + size
40*5bd9c17dSSaurabh Gorecha 			|| (BL31_BASE < addr + size && BL31_LIMIT > addr)) {
41*5bd9c17dSSaurabh Gorecha 		return true;
42*5bd9c17dSSaurabh Gorecha 	}
43*5bd9c17dSSaurabh Gorecha 	return false;
44*5bd9c17dSSaurabh Gorecha }
45*5bd9c17dSSaurabh Gorecha 
46*5bd9c17dSSaurabh Gorecha /*
47*5bd9c17dSSaurabh Gorecha  *  unsigned int plat_qti_my_cluster_pos(void)
48*5bd9c17dSSaurabh Gorecha  *  definition to get the cluster index of the calling CPU.
49*5bd9c17dSSaurabh Gorecha  *  - In ARM v8   (MPIDR_EL1[24]=0)
50*5bd9c17dSSaurabh Gorecha  *    ClusterId = MPIDR_EL1[15:8]
51*5bd9c17dSSaurabh Gorecha  *  - In ARM v8.1 & Later version (MPIDR_EL1[24]=1)
52*5bd9c17dSSaurabh Gorecha  *    ClusterId = MPIDR_EL1[23:15]
53*5bd9c17dSSaurabh Gorecha  */
54*5bd9c17dSSaurabh Gorecha unsigned int plat_qti_my_cluster_pos(void)
55*5bd9c17dSSaurabh Gorecha {
56*5bd9c17dSSaurabh Gorecha 	unsigned int mpidr, cluster_id;
57*5bd9c17dSSaurabh Gorecha 
58*5bd9c17dSSaurabh Gorecha 	mpidr = read_mpidr_el1();
59*5bd9c17dSSaurabh Gorecha 	if ((mpidr & MPIDR_MT_MASK) == 0) {	/* MT not supported */
60*5bd9c17dSSaurabh Gorecha 		cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
61*5bd9c17dSSaurabh Gorecha 	} else {		/* MT supported */
62*5bd9c17dSSaurabh Gorecha 		cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
63*5bd9c17dSSaurabh Gorecha 	}
64*5bd9c17dSSaurabh Gorecha 	assert(cluster_id < PLAT_CLUSTER_COUNT);
65*5bd9c17dSSaurabh Gorecha 	return cluster_id;
66*5bd9c17dSSaurabh Gorecha }
67*5bd9c17dSSaurabh Gorecha 
68*5bd9c17dSSaurabh Gorecha /*
69*5bd9c17dSSaurabh Gorecha  * Set up the page tables for the generic and platform-specific memory regions.
70*5bd9c17dSSaurabh Gorecha  * The extents of the generic memory regions are specified by the function
71*5bd9c17dSSaurabh Gorecha  * arguments and consist of:
72*5bd9c17dSSaurabh Gorecha  * - Trusted SRAM seen by the BL image;
73*5bd9c17dSSaurabh Gorecha  * - Code section;
74*5bd9c17dSSaurabh Gorecha  * - Read-only data section;
75*5bd9c17dSSaurabh Gorecha  * - Coherent memory region, if applicable.
76*5bd9c17dSSaurabh Gorecha  */
77*5bd9c17dSSaurabh Gorecha void qti_setup_page_tables(uintptr_t total_base,
78*5bd9c17dSSaurabh Gorecha 			   size_t total_size,
79*5bd9c17dSSaurabh Gorecha 			   uintptr_t code_start,
80*5bd9c17dSSaurabh Gorecha 			   uintptr_t code_limit,
81*5bd9c17dSSaurabh Gorecha 			   uintptr_t rodata_start,
82*5bd9c17dSSaurabh Gorecha 			   uintptr_t rodata_limit,
83*5bd9c17dSSaurabh Gorecha 			   uintptr_t coh_start, uintptr_t coh_limit)
84*5bd9c17dSSaurabh Gorecha {
85*5bd9c17dSSaurabh Gorecha 	/*
86*5bd9c17dSSaurabh Gorecha 	 * Map the Trusted SRAM with appropriate memory attributes.
87*5bd9c17dSSaurabh Gorecha 	 * Subsequent mappings will adjust the attributes for specific regions.
88*5bd9c17dSSaurabh Gorecha 	 */
89*5bd9c17dSSaurabh Gorecha 	VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
90*5bd9c17dSSaurabh Gorecha 		(void *)total_base, (void *)(total_base + total_size));
91*5bd9c17dSSaurabh Gorecha 	mmap_add_region(total_base, total_base,
92*5bd9c17dSSaurabh Gorecha 			total_size, MT_MEMORY | MT_RW | MT_SECURE);
93*5bd9c17dSSaurabh Gorecha 
94*5bd9c17dSSaurabh Gorecha 	/* Re-map the code section */
95*5bd9c17dSSaurabh Gorecha 	VERBOSE("Code region: %p - %p\n",
96*5bd9c17dSSaurabh Gorecha 		(void *)code_start, (void *)code_limit);
97*5bd9c17dSSaurabh Gorecha 	mmap_add_region(code_start, code_start,
98*5bd9c17dSSaurabh Gorecha 			code_limit - code_start, MT_CODE | MT_SECURE);
99*5bd9c17dSSaurabh Gorecha 
100*5bd9c17dSSaurabh Gorecha 	/* Re-map the read-only data section */
101*5bd9c17dSSaurabh Gorecha 	VERBOSE("Read-only data region: %p - %p\n",
102*5bd9c17dSSaurabh Gorecha 		(void *)rodata_start, (void *)rodata_limit);
103*5bd9c17dSSaurabh Gorecha 	mmap_add_region(rodata_start, rodata_start,
104*5bd9c17dSSaurabh Gorecha 			rodata_limit - rodata_start, MT_RO_DATA | MT_SECURE);
105*5bd9c17dSSaurabh Gorecha 
106*5bd9c17dSSaurabh Gorecha 	/* Re-map the coherent memory region */
107*5bd9c17dSSaurabh Gorecha 	VERBOSE("Coherent region: %p - %p\n",
108*5bd9c17dSSaurabh Gorecha 		(void *)coh_start, (void *)coh_limit);
109*5bd9c17dSSaurabh Gorecha 	mmap_add_region(coh_start, coh_start,
110*5bd9c17dSSaurabh Gorecha 			coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE);
111*5bd9c17dSSaurabh Gorecha 
112*5bd9c17dSSaurabh Gorecha 	/* Now (re-)map the platform-specific memory regions */
113*5bd9c17dSSaurabh Gorecha 	mmap_add(plat_qti_mmap);
114*5bd9c17dSSaurabh Gorecha 
115*5bd9c17dSSaurabh Gorecha 	/* Create the page tables to reflect the above mappings */
116*5bd9c17dSSaurabh Gorecha 	init_xlat_tables();
117*5bd9c17dSSaurabh Gorecha }
118*5bd9c17dSSaurabh Gorecha 
119*5bd9c17dSSaurabh Gorecha static inline void qti_align_mem_region(uintptr_t addr, size_t size,
120*5bd9c17dSSaurabh Gorecha 					uintptr_t *aligned_addr,
121*5bd9c17dSSaurabh Gorecha 					size_t *aligned_size)
122*5bd9c17dSSaurabh Gorecha {
123*5bd9c17dSSaurabh Gorecha 	*aligned_addr = round_down(addr, PAGE_SIZE);
124*5bd9c17dSSaurabh Gorecha 	*aligned_size = round_up(addr - *aligned_addr + size, PAGE_SIZE);
125*5bd9c17dSSaurabh Gorecha }
126*5bd9c17dSSaurabh Gorecha 
127*5bd9c17dSSaurabh Gorecha int qti_mmap_add_dynamic_region(uintptr_t base_pa, size_t size,
128*5bd9c17dSSaurabh Gorecha 				unsigned int attr)
129*5bd9c17dSSaurabh Gorecha {
130*5bd9c17dSSaurabh Gorecha 	uintptr_t aligned_pa;
131*5bd9c17dSSaurabh Gorecha 	size_t aligned_size;
132*5bd9c17dSSaurabh Gorecha 
133*5bd9c17dSSaurabh Gorecha 	qti_align_mem_region(base_pa, size, &aligned_pa, &aligned_size);
134*5bd9c17dSSaurabh Gorecha 
135*5bd9c17dSSaurabh Gorecha 	if (qti_is_overlap_atf_rg(base_pa, size)) {
136*5bd9c17dSSaurabh Gorecha 		/* Memory shouldn't overlap with TF-A range. */
137*5bd9c17dSSaurabh Gorecha 		return -EPERM;
138*5bd9c17dSSaurabh Gorecha 	}
139*5bd9c17dSSaurabh Gorecha 
140*5bd9c17dSSaurabh Gorecha 	return mmap_add_dynamic_region(aligned_pa, aligned_pa, aligned_size,
141*5bd9c17dSSaurabh Gorecha 				       attr);
142*5bd9c17dSSaurabh Gorecha }
143*5bd9c17dSSaurabh Gorecha 
144*5bd9c17dSSaurabh Gorecha int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
145*5bd9c17dSSaurabh Gorecha {
146*5bd9c17dSSaurabh Gorecha 	qti_align_mem_region(base_va, size, &base_va, &size);
147*5bd9c17dSSaurabh Gorecha 	return mmap_remove_dynamic_region(base_va, size);
148*5bd9c17dSSaurabh Gorecha }
149