1*c48d0aefSSumit Garg /* 2*c48d0aefSSumit Garg * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. 3*c48d0aefSSumit Garg * 4*c48d0aefSSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5*c48d0aefSSumit Garg */ 6*c48d0aefSSumit Garg 7*c48d0aefSSumit Garg #include <errno.h> 8*c48d0aefSSumit Garg 9*c48d0aefSSumit Garg #include <common/bl_common.h> 10*c48d0aefSSumit Garg #include <common/debug.h> 11*c48d0aefSSumit Garg #include <common/desc_image_load.h> 12*c48d0aefSSumit Garg #include <common/image_decompress.h> 13*c48d0aefSSumit Garg #include <drivers/io/io_storage.h> 14*c48d0aefSSumit Garg #include <lib/xlat_tables/xlat_tables_v2.h> 15*c48d0aefSSumit Garg #include <plat/common/platform.h> 16*c48d0aefSSumit Garg 17*c48d0aefSSumit Garg #include <platform_def.h> 18*c48d0aefSSumit Garg #include <qti_plat.h> 19*c48d0aefSSumit Garg #include <qti_uart_console.h> 20*c48d0aefSSumit Garg 21*c48d0aefSSumit Garg static console_t g_qti_console_uart; 22*c48d0aefSSumit Garg 23*c48d0aefSSumit Garg void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 24*c48d0aefSSumit Garg u_register_t x2, u_register_t x3) 25*c48d0aefSSumit Garg { 26*c48d0aefSSumit Garg qti_console_uart_register(&g_qti_console_uart, 27*c48d0aefSSumit Garg PLAT_QTI_UART_BASE); 28*c48d0aefSSumit Garg console_set_scope(&g_qti_console_uart, 29*c48d0aefSSumit Garg CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH); 30*c48d0aefSSumit Garg } 31*c48d0aefSSumit Garg 32*c48d0aefSSumit Garg void bl2_el3_plat_arch_setup(void) 33*c48d0aefSSumit Garg { 34*c48d0aefSSumit Garg int ret; 35*c48d0aefSSumit Garg 36*c48d0aefSSumit Garg qti_setup_page_tables(BL2_BASE, 37*c48d0aefSSumit Garg BL2_SIZE, 38*c48d0aefSSumit Garg BL_CODE_BASE, 39*c48d0aefSSumit Garg BL_CODE_END, 40*c48d0aefSSumit Garg BL_RO_DATA_BASE, 41*c48d0aefSSumit Garg BL_RO_DATA_END); 42*c48d0aefSSumit Garg enable_mmu_el3(0); 43*c48d0aefSSumit Garg 44*c48d0aefSSumit Garg ret = qti_io_setup(); 45*c48d0aefSSumit Garg if (ret) { 46*c48d0aefSSumit Garg ERROR("failed to setup io devices\n"); 47*c48d0aefSSumit Garg plat_error_handler(ret); 48*c48d0aefSSumit Garg } 49*c48d0aefSSumit Garg } 50*c48d0aefSSumit Garg 51*c48d0aefSSumit Garg void bl2_platform_setup(void) 52*c48d0aefSSumit Garg { 53*c48d0aefSSumit Garg } 54*c48d0aefSSumit Garg 55*c48d0aefSSumit Garg void plat_flush_next_bl_params(void) 56*c48d0aefSSumit Garg { 57*c48d0aefSSumit Garg flush_bl_params_desc(); 58*c48d0aefSSumit Garg } 59*c48d0aefSSumit Garg 60*c48d0aefSSumit Garg bl_load_info_t *plat_get_bl_image_load_info(void) 61*c48d0aefSSumit Garg { 62*c48d0aefSSumit Garg return get_bl_load_info_from_mem_params_desc(); 63*c48d0aefSSumit Garg } 64*c48d0aefSSumit Garg 65*c48d0aefSSumit Garg bl_params_t *plat_get_next_bl_params(void) 66*c48d0aefSSumit Garg { 67*c48d0aefSSumit Garg return get_next_bl_params_from_mem_params_desc(); 68*c48d0aefSSumit Garg } 69*c48d0aefSSumit Garg 70*c48d0aefSSumit Garg void bl2_plat_preload_setup(void) 71*c48d0aefSSumit Garg { 72*c48d0aefSSumit Garg } 73*c48d0aefSSumit Garg 74*c48d0aefSSumit Garg int bl2_plat_handle_pre_image_load(unsigned int image_id) 75*c48d0aefSSumit Garg { 76*c48d0aefSSumit Garg struct image_info *image_info; 77*c48d0aefSSumit Garg 78*c48d0aefSSumit Garg image_info = qti_get_image_info(image_id); 79*c48d0aefSSumit Garg 80*c48d0aefSSumit Garg return mmap_add_dynamic_region(image_info->image_base, 81*c48d0aefSSumit Garg image_info->image_base, 82*c48d0aefSSumit Garg image_info->image_max_size, 83*c48d0aefSSumit Garg MT_MEMORY | MT_RW | MT_NS); 84*c48d0aefSSumit Garg } 85*c48d0aefSSumit Garg 86*c48d0aefSSumit Garg int bl2_plat_handle_post_image_load(unsigned int image_id) 87*c48d0aefSSumit Garg { 88*c48d0aefSSumit Garg return 0; 89*c48d0aefSSumit Garg } 90