1*b8a05116SShelley Chen /* 2*b8a05116SShelley Chen * Copyright (c) 2020, Google LLC. All rights reserved. 3*b8a05116SShelley Chen * 4*b8a05116SShelley Chen * SPDX-License-Identifier: BSD-3-Clause 5*b8a05116SShelley Chen */ 6*b8a05116SShelley Chen 7*b8a05116SShelley Chen #include <drivers/delay_timer.h> 8*b8a05116SShelley Chen 9*b8a05116SShelley Chen #include <qti_plat.h> 10*b8a05116SShelley Chen #include <spmi_arb.h> 11*b8a05116SShelley Chen 12*b8a05116SShelley Chen /* 13*b8a05116SShelley Chen * This driver implements PON support for PM8998-compatible PMICs. This can 14*b8a05116SShelley Chen * include other part numbers like PM6150. 15*b8a05116SShelley Chen */ 16*b8a05116SShelley Chen 17*b8a05116SShelley Chen #define RESET_TYPE_WARM_RESET 1 18*b8a05116SShelley Chen #define RESET_TYPE_SHUTDOWN 4 19*b8a05116SShelley Chen 20*b8a05116SShelley Chen #define S2_RESET_EN BIT(7) 21*b8a05116SShelley Chen configure_ps_hold(uint32_t reset_type)22*b8a05116SShelley Chenstatic void configure_ps_hold(uint32_t reset_type) 23*b8a05116SShelley Chen { 24*b8a05116SShelley Chen /* QTI recommends disabling reset for 10 cycles before reconfiguring. */ 25*b8a05116SShelley Chen spmi_arb_write8(PON_PS_HOLD_RESET_CTL2, 0); 26*b8a05116SShelley Chen mdelay(1); 27*b8a05116SShelley Chen 28*b8a05116SShelley Chen spmi_arb_write8(PON_PS_HOLD_RESET_CTL, reset_type); 29*b8a05116SShelley Chen spmi_arb_write8(PON_PS_HOLD_RESET_CTL2, S2_RESET_EN); 30*b8a05116SShelley Chen mdelay(1); 31*b8a05116SShelley Chen } 32*b8a05116SShelley Chen qti_pmic_prepare_reset(void)33*b8a05116SShelley Chenvoid qti_pmic_prepare_reset(void) 34*b8a05116SShelley Chen { 35*b8a05116SShelley Chen configure_ps_hold(RESET_TYPE_WARM_RESET); 36*b8a05116SShelley Chen } 37*b8a05116SShelley Chen qti_pmic_prepare_shutdown(void)38*b8a05116SShelley Chenvoid qti_pmic_prepare_shutdown(void) 39*b8a05116SShelley Chen { 40*b8a05116SShelley Chen configure_ps_hold(RESET_TYPE_SHUTDOWN); 41*b8a05116SShelley Chen } 42