1*5bd9c17dSSaurabh Gorecha/* 2*5bd9c17dSSaurabh Gorecha * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3*5bd9c17dSSaurabh Gorecha * Copyright (c) 2018,2020, The Linux Foundation. All rights reserved. 4*5bd9c17dSSaurabh Gorecha * 5*5bd9c17dSSaurabh Gorecha * SPDX-License-Identifier: BSD-3-Clause 6*5bd9c17dSSaurabh Gorecha */ 7*5bd9c17dSSaurabh Gorecha 8*5bd9c17dSSaurabh Gorecha#include <arch.h> 9*5bd9c17dSSaurabh Gorecha#include <asm_macros.S> 10*5bd9c17dSSaurabh Gorecha#include <drivers/arm/gicv2.h> 11*5bd9c17dSSaurabh Gorecha#include <drivers/arm/gicv3.h> 12*5bd9c17dSSaurabh Gorecha#include <drivers/console.h> 13*5bd9c17dSSaurabh Gorecha 14*5bd9c17dSSaurabh Gorecha#include <platform_def.h> 15*5bd9c17dSSaurabh Gorecha 16*5bd9c17dSSaurabh Gorecha .globl plat_my_core_pos 17*5bd9c17dSSaurabh Gorecha .globl plat_qti_core_pos_by_mpidr 18*5bd9c17dSSaurabh Gorecha .globl plat_reset_handler 19*5bd9c17dSSaurabh Gorecha .globl plat_panic_handler 20*5bd9c17dSSaurabh Gorecha 21*5bd9c17dSSaurabh Gorecha /* ----------------------------------------------------- 22*5bd9c17dSSaurabh Gorecha * unsigned int plat_qti_core_pos_by_mpidr(uint64_t mpidr) 23*5bd9c17dSSaurabh Gorecha * Helper function to calculate the core position. 24*5bd9c17dSSaurabh Gorecha * With this function: 25*5bd9c17dSSaurabh Gorecha * CorePos = (ClusterId * 4) + CoreId 26*5bd9c17dSSaurabh Gorecha * - In ARM v8 (MPIDR_EL1[24]=0) 27*5bd9c17dSSaurabh Gorecha * ClusterId = MPIDR_EL1[15:8] 28*5bd9c17dSSaurabh Gorecha * CoreId = MPIDR_EL1[7:0] 29*5bd9c17dSSaurabh Gorecha * - In ARM v8.1 (MPIDR_EL1[24]=1) 30*5bd9c17dSSaurabh Gorecha * ClusterId = MPIDR_EL1[23:15] 31*5bd9c17dSSaurabh Gorecha * CoreId = MPIDR_EL1[15:8] 32*5bd9c17dSSaurabh Gorecha * Clobbers: x0 & x1. 33*5bd9c17dSSaurabh Gorecha * ----------------------------------------------------- 34*5bd9c17dSSaurabh Gorecha */ 35*5bd9c17dSSaurabh Gorechafunc plat_qti_core_pos_by_mpidr 36*5bd9c17dSSaurabh Gorecha mrs x1, mpidr_el1 37*5bd9c17dSSaurabh Gorecha tst x1, #MPIDR_MT_MASK 38*5bd9c17dSSaurabh Gorecha beq plat_qti_core_pos_by_mpidr_no_mt 39*5bd9c17dSSaurabh Gorecha /* Right shift mpidr by one affinity level when MT=1. */ 40*5bd9c17dSSaurabh Gorecha lsr x0, x0, #MPIDR_AFFINITY_BITS 41*5bd9c17dSSaurabh Gorechaplat_qti_core_pos_by_mpidr_no_mt: 42*5bd9c17dSSaurabh Gorecha and x1, x0, #MPIDR_CPU_MASK 43*5bd9c17dSSaurabh Gorecha and x0, x0, #MPIDR_CLUSTER_MASK 44*5bd9c17dSSaurabh Gorecha add x0, x1, x0, LSR #6 45*5bd9c17dSSaurabh Gorecha ret 46*5bd9c17dSSaurabh Gorechaendfunc plat_qti_core_pos_by_mpidr 47*5bd9c17dSSaurabh Gorecha 48*5bd9c17dSSaurabh Gorecha /* -------------------------------------------------------------------- 49*5bd9c17dSSaurabh Gorecha * void plat_panic_handler(void) 50*5bd9c17dSSaurabh Gorecha * calls SDI and reset system 51*5bd9c17dSSaurabh Gorecha * -------------------------------------------------------------------- 52*5bd9c17dSSaurabh Gorecha */ 53*5bd9c17dSSaurabh Gorechafunc plat_panic_handler 54*5bd9c17dSSaurabh Gorecha msr spsel, #0 55*5bd9c17dSSaurabh Gorecha bl plat_set_my_stack 56*5bd9c17dSSaurabh Gorecha b qtiseclib_panic 57*5bd9c17dSSaurabh Gorechaendfunc plat_panic_handler 58*5bd9c17dSSaurabh Gorecha 59*5bd9c17dSSaurabh Gorecha /* ----------------------------------------------------- 60*5bd9c17dSSaurabh Gorecha * unsigned int plat_my_core_pos(void) 61*5bd9c17dSSaurabh Gorecha * This function uses the plat_qti_calc_core_pos() 62*5bd9c17dSSaurabh Gorecha * definition to get the index of the calling CPU 63*5bd9c17dSSaurabh Gorecha * Clobbers: x0 & x1. 64*5bd9c17dSSaurabh Gorecha * ----------------------------------------------------- 65*5bd9c17dSSaurabh Gorecha */ 66*5bd9c17dSSaurabh Gorechafunc plat_my_core_pos 67*5bd9c17dSSaurabh Gorecha mrs x0, mpidr_el1 68*5bd9c17dSSaurabh Gorecha b plat_qti_core_pos_by_mpidr 69*5bd9c17dSSaurabh Gorechaendfunc plat_my_core_pos 70*5bd9c17dSSaurabh Gorecha 71*5bd9c17dSSaurabh Gorechafunc plat_reset_handler 72*5bd9c17dSSaurabh Gorecha /* save the lr */ 73*5bd9c17dSSaurabh Gorecha mov x18, x30 74*5bd9c17dSSaurabh Gorecha 75*5bd9c17dSSaurabh Gorecha /* pass cold boot status. */ 76*5bd9c17dSSaurabh Gorecha ldr w0, g_qti_bl31_cold_booted 77*5bd9c17dSSaurabh Gorecha /* Execuete CPUSS boot set up on every core. */ 78*5bd9c17dSSaurabh Gorecha bl qtiseclib_cpuss_reset_asm 79*5bd9c17dSSaurabh Gorecha 80*5bd9c17dSSaurabh Gorecha ret x18 81*5bd9c17dSSaurabh Gorechaendfunc plat_reset_handler 82