1*5bd9c17dSSaurabh Gorecha /* 2*5bd9c17dSSaurabh Gorecha * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*5bd9c17dSSaurabh Gorecha * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4*5bd9c17dSSaurabh Gorecha * 5*5bd9c17dSSaurabh Gorecha * SPDX-License-Identifier: BSD-3-Clause 6*5bd9c17dSSaurabh Gorecha */ 7*5bd9c17dSSaurabh Gorecha #ifndef QTI_BOARD_DEF_H 8*5bd9c17dSSaurabh Gorecha #define QTI_BOARD_DEF_H 9*5bd9c17dSSaurabh Gorecha 10*5bd9c17dSSaurabh Gorecha /* 11*5bd9c17dSSaurabh Gorecha * Required platform porting definitions common to all ARM 12*5bd9c17dSSaurabh Gorecha * development platforms 13*5bd9c17dSSaurabh Gorecha */ 14*5bd9c17dSSaurabh Gorecha 15*5bd9c17dSSaurabh Gorecha /* Size of cacheable stacks */ 16*5bd9c17dSSaurabh Gorecha #define PLATFORM_STACK_SIZE 0x1000 17*5bd9c17dSSaurabh Gorecha 18*5bd9c17dSSaurabh Gorecha /* 19*5bd9c17dSSaurabh Gorecha * PLAT_QTI_MMAP_ENTRIES depends on the number of entries in the 20*5bd9c17dSSaurabh Gorecha * plat_qti_mmap array defined for each BL stage. 21*5bd9c17dSSaurabh Gorecha */ 22*5bd9c17dSSaurabh Gorecha #define PLAT_QTI_MMAP_ENTRIES 12 23*5bd9c17dSSaurabh Gorecha 24*5bd9c17dSSaurabh Gorecha /* 25*5bd9c17dSSaurabh Gorecha * Platform specific page table and MMU setup constants 26*5bd9c17dSSaurabh Gorecha */ 27*5bd9c17dSSaurabh Gorecha #define MAX_XLAT_TABLES 12 28*5bd9c17dSSaurabh Gorecha 29*5bd9c17dSSaurabh Gorecha #endif /* QTI_BOARD_DEF_H */ 30