1 /* 2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/fdt_wrappers.h> 10 #include <common/runtime_svc.h> 11 #include <libfdt.h> 12 #include <smccc_helpers.h> 13 14 /* default platform version is 0.0 */ 15 static int platform_version_major; 16 static int platform_version_minor; 17 18 #define SMC_FASTCALL 0x80000000 19 #define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000) 20 #define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000) 21 #define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n)) 22 23 /* 24 * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform 25 * which uses SoC present in QEMU. And they can change on their own while we 26 * need version of whole 'virtual hardware platform'. 27 */ 28 #define SIP_SVC_VERSION SIP_FUNCTION_ID(1) 29 #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100) 30 #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101) 31 #define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200) 32 #define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201) 33 34 static uint64_t gic_its_addr; 35 36 typedef struct { 37 uint32_t nodeid; 38 uint32_t mpidr; 39 } cpu_data; 40 41 static struct { 42 uint32_t num_cpus; 43 cpu_data cpu[PLATFORM_CORE_COUNT]; 44 } dynamic_platform_info; 45 46 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base); 47 uintptr_t sbsa_get_gicd(void); 48 uintptr_t sbsa_get_gicr(void); 49 50 /* 51 * QEMU provides us with minimal information about hardware platform using 52 * minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even 53 * a firmware DeviceTree. 54 * 55 * It is information passed from QEMU to describe the information a hardware 56 * platform would have other mechanisms to discover at runtime, that are 57 * affected by the QEMU command line. 58 * 59 * Ultimately this device tree will be replaced by IPC calls to an emulated SCP. 60 * And when we do that, we won't then have to rewrite Normal world firmware to 61 * cope. 62 */ 63 64 void read_cpuinfo_from_dt(void *dtb) 65 { 66 int node; 67 int prev; 68 int cpu = 0; 69 uint32_t nodeid = 0; 70 uintptr_t mpidr; 71 72 /* 73 * QEMU gives us this DeviceTree node: 74 * numa-node-id entries are only when NUMA config is used 75 * 76 * cpus { 77 * #size-cells = <0x00>; 78 * #address-cells = <0x02>; 79 * 80 * cpu@0 { 81 * numa-node-id = <0x00>; 82 * reg = <0x00 0x00>; 83 * }; 84 * 85 * cpu@1 { 86 * numa-node-id = <0x03>; 87 * reg = <0x00 0x01>; 88 * }; 89 * }; 90 */ 91 node = fdt_path_offset(dtb, "/cpus"); 92 if (node < 0) { 93 ERROR("No information about cpus in DeviceTree.\n"); 94 panic(); 95 } 96 97 /* 98 * QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we 99 * cannot use fdt_first_subnode() here 100 */ 101 node = fdt_path_offset(dtb, "/cpus/cpu@0"); 102 103 while (node > 0) { 104 if (fdt_getprop(dtb, node, "reg", NULL)) { 105 fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL); 106 } else { 107 ERROR("Incomplete information for cpu %d in DeviceTree.\n", cpu); 108 panic(); 109 } 110 111 if (fdt_getprop(dtb, node, "numa-node-id", NULL)) { 112 fdt_read_uint32(dtb, node, "numa-node-id", &nodeid); 113 } 114 115 dynamic_platform_info.cpu[cpu].nodeid = nodeid; 116 dynamic_platform_info.cpu[cpu].mpidr = mpidr; 117 118 INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, nodeid, mpidr); 119 120 cpu++; 121 122 prev = node; 123 node = fdt_next_subnode(dtb, prev); 124 } 125 126 dynamic_platform_info.num_cpus = cpu; 127 INFO("Found %d cpus\n", dynamic_platform_info.num_cpus); 128 } 129 130 void read_platform_config_from_dt(void *dtb) 131 { 132 int node; 133 const fdt64_t *data; 134 int err; 135 uintptr_t gicd_base; 136 uintptr_t gicr_base; 137 138 /* 139 * QEMU gives us this DeviceTree node: 140 * 141 * intc { 142 * reg = < 0x00 0x40060000 0x00 0x10000 143 * 0x00 0x40080000 0x00 0x4000000>; 144 * its { 145 * reg = <0x00 0x44081000 0x00 0x20000>; 146 * }; 147 * }; 148 */ 149 node = fdt_path_offset(dtb, "/intc"); 150 if (node < 0) { 151 return; 152 } 153 154 data = fdt_getprop(dtb, node, "reg", NULL); 155 if (data == NULL) { 156 return; 157 } 158 159 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL); 160 if (err < 0) { 161 ERROR("Failed to read GICD reg property of GIC node\n"); 162 return; 163 } 164 INFO("GICD base = 0x%lx\n", gicd_base); 165 166 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL); 167 if (err < 0) { 168 ERROR("Failed to read GICR reg property of GIC node\n"); 169 return; 170 } 171 INFO("GICR base = 0x%lx\n", gicr_base); 172 173 sbsa_set_gic_bases(gicd_base, gicr_base); 174 175 node = fdt_path_offset(dtb, "/intc/its"); 176 if (node < 0) { 177 return; 178 } 179 180 err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL); 181 if (err < 0) { 182 ERROR("Failed to read GICI reg property of GIC node\n"); 183 return; 184 } 185 INFO("GICI base = 0x%lx\n", gic_its_addr); 186 } 187 188 void read_platform_version(void *dtb) 189 { 190 int node; 191 192 node = fdt_path_offset(dtb, "/"); 193 if (node >= 0) { 194 platform_version_major = fdt32_ld(fdt_getprop(dtb, node, 195 "machine-version-major", NULL)); 196 platform_version_minor = fdt32_ld(fdt_getprop(dtb, node, 197 "machine-version-minor", NULL)); 198 } 199 } 200 201 void sip_svc_init(void) 202 { 203 /* Read DeviceTree data before MMU is enabled */ 204 205 void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; 206 int err; 207 208 err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE); 209 if (err < 0) { 210 ERROR("Invalid Device Tree at %p: error %d\n", dtb, err); 211 return; 212 } 213 214 err = fdt_check_header(dtb); 215 if (err < 0) { 216 ERROR("Invalid DTB file passed\n"); 217 return; 218 } 219 220 read_platform_version(dtb); 221 INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor); 222 223 read_platform_config_from_dt(dtb); 224 read_cpuinfo_from_dt(dtb); 225 } 226 227 /* 228 * This function is responsible for handling all SiP calls from the NS world 229 */ 230 uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid, 231 u_register_t x1, 232 u_register_t x2, 233 u_register_t x3, 234 u_register_t x4, 235 void *cookie, 236 void *handle, 237 u_register_t flags) 238 { 239 uint32_t ns; 240 uint64_t index; 241 242 /* Determine which security state this SMC originated from */ 243 ns = is_caller_non_secure(flags); 244 if (!ns) { 245 ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid); 246 SMC_RET1(handle, SMC_UNK); 247 } 248 249 switch (smc_fid) { 250 case SIP_SVC_VERSION: 251 INFO("Platform version requested\n"); 252 SMC_RET3(handle, NULL, platform_version_major, platform_version_minor); 253 254 case SIP_SVC_GET_GIC: 255 SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr()); 256 257 case SIP_SVC_GET_GIC_ITS: 258 SMC_RET2(handle, NULL, gic_its_addr); 259 260 case SIP_SVC_GET_CPU_COUNT: 261 SMC_RET2(handle, NULL, dynamic_platform_info.num_cpus); 262 263 case SIP_SVC_GET_CPU_NODE: 264 index = x1; 265 if (index < PLATFORM_CORE_COUNT) { 266 SMC_RET3(handle, NULL, 267 dynamic_platform_info.cpu[index].nodeid, 268 dynamic_platform_info.cpu[index].mpidr); 269 } else { 270 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM); 271 } 272 273 default: 274 ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid, 275 smc_fid - SIP_FUNCTION); 276 SMC_RET1(handle, SMC_UNK); 277 } 278 } 279 280 int sbsa_sip_smc_setup(void) 281 { 282 return 0; 283 } 284 285 /* Define a runtime service descriptor for fast SMC calls */ 286 DECLARE_RT_SVC( 287 sbsa_sip_svc, 288 OEN_SIP_START, 289 OEN_SIP_END, 290 SMC_TYPE_FAST, 291 sbsa_sip_smc_setup, 292 sbsa_sip_smc_handler 293 ); 294