1 /* 2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/fdt_wrappers.h> 10 #include <common/runtime_svc.h> 11 #include <libfdt.h> 12 #include <smccc_helpers.h> 13 14 /* default platform version is 0.0 */ 15 static int platform_version_major; 16 static int platform_version_minor; 17 18 #define SMC_FASTCALL 0x80000000 19 #define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000) 20 #define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000) 21 #define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n)) 22 23 /* 24 * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform 25 * which uses SoC present in QEMU. And they can change on their own while we 26 * need version of whole 'virtual hardware platform'. 27 */ 28 #define SIP_SVC_VERSION SIP_FUNCTION_ID(1) 29 #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100) 30 #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101) 31 #define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200) 32 #define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201) 33 34 static uint64_t gic_its_addr; 35 36 typedef struct { 37 uint32_t nodeid; 38 uint32_t mpidr; 39 } cpu_data; 40 41 static struct { 42 uint32_t num_cpus; 43 cpu_data cpu[PLATFORM_CORE_COUNT]; 44 } dynamic_platform_info; 45 46 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base); 47 uintptr_t sbsa_get_gicd(void); 48 uintptr_t sbsa_get_gicr(void); 49 50 /* 51 * QEMU provides us with minimal information about hardware platform using 52 * minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even 53 * a firmware DeviceTree. 54 * 55 * It is information passed from QEMU to describe the information a hardware 56 * platform would have other mechanisms to discover at runtime, that are 57 * affected by the QEMU command line. 58 * 59 * Ultimately this device tree will be replaced by IPC calls to an emulated SCP. 60 * And when we do that, we won't then have to rewrite Normal world firmware to 61 * cope. 62 */ 63 64 void read_cpuinfo_from_dt(void *dtb) 65 { 66 int node; 67 int prev; 68 int cpu = 0; 69 uint32_t nodeid = 0; 70 uintptr_t mpidr; 71 72 /* 73 * QEMU gives us this DeviceTree node: 74 * numa-node-id entries are only when NUMA config is used 75 * 76 * cpus { 77 * #size-cells = <0x00>; 78 * #address-cells = <0x02>; 79 * 80 * cpu@0 { 81 * numa-node-id = <0x00>; 82 * reg = <0x00 0x00>; 83 * }; 84 * 85 * cpu@1 { 86 * numa-node-id = <0x03>; 87 * reg = <0x00 0x01>; 88 * }; 89 * }; 90 */ 91 node = fdt_path_offset(dtb, "/cpus"); 92 if (node < 0) { 93 ERROR("No information about cpus in DeviceTree.\n"); 94 panic(); 95 } 96 97 /* 98 * QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we 99 * cannot use fdt_first_subnode() here 100 */ 101 node = fdt_path_offset(dtb, "/cpus/cpu@0"); 102 103 while (node > 0) { 104 if (fdt_getprop(dtb, node, "reg", NULL)) { 105 fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL); 106 } 107 108 if (fdt_getprop(dtb, node, "numa-node-id", NULL)) { 109 fdt_read_uint32(dtb, node, "numa-node-id", &nodeid); 110 } 111 112 dynamic_platform_info.cpu[cpu].nodeid = nodeid; 113 dynamic_platform_info.cpu[cpu].mpidr = mpidr; 114 115 INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, nodeid, mpidr); 116 117 cpu++; 118 119 prev = node; 120 node = fdt_next_subnode(dtb, prev); 121 } 122 123 dynamic_platform_info.num_cpus = cpu; 124 INFO("Found %d cpus\n", dynamic_platform_info.num_cpus); 125 } 126 127 void read_platform_config_from_dt(void *dtb) 128 { 129 int node; 130 const fdt64_t *data; 131 int err; 132 uintptr_t gicd_base; 133 uintptr_t gicr_base; 134 135 /* 136 * QEMU gives us this DeviceTree node: 137 * 138 * intc { 139 * reg = < 0x00 0x40060000 0x00 0x10000 140 * 0x00 0x40080000 0x00 0x4000000>; 141 * its { 142 * reg = <0x00 0x44081000 0x00 0x20000>; 143 * }; 144 * }; 145 */ 146 node = fdt_path_offset(dtb, "/intc"); 147 if (node < 0) { 148 return; 149 } 150 151 data = fdt_getprop(dtb, node, "reg", NULL); 152 if (data == NULL) { 153 return; 154 } 155 156 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL); 157 if (err < 0) { 158 ERROR("Failed to read GICD reg property of GIC node\n"); 159 return; 160 } 161 INFO("GICD base = 0x%lx\n", gicd_base); 162 163 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL); 164 if (err < 0) { 165 ERROR("Failed to read GICR reg property of GIC node\n"); 166 return; 167 } 168 INFO("GICR base = 0x%lx\n", gicr_base); 169 170 sbsa_set_gic_bases(gicd_base, gicr_base); 171 172 node = fdt_path_offset(dtb, "/intc/its"); 173 if (node < 0) { 174 return; 175 } 176 177 err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL); 178 if (err < 0) { 179 ERROR("Failed to read GICI reg property of GIC node\n"); 180 return; 181 } 182 INFO("GICI base = 0x%lx\n", gic_its_addr); 183 } 184 185 void read_platform_version(void *dtb) 186 { 187 int node; 188 189 node = fdt_path_offset(dtb, "/"); 190 if (node >= 0) { 191 platform_version_major = fdt32_ld(fdt_getprop(dtb, node, 192 "machine-version-major", NULL)); 193 platform_version_minor = fdt32_ld(fdt_getprop(dtb, node, 194 "machine-version-minor", NULL)); 195 } 196 } 197 198 void sip_svc_init(void) 199 { 200 /* Read DeviceTree data before MMU is enabled */ 201 202 void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; 203 int err; 204 205 err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE); 206 if (err < 0) { 207 ERROR("Invalid Device Tree at %p: error %d\n", dtb, err); 208 return; 209 } 210 211 err = fdt_check_header(dtb); 212 if (err < 0) { 213 ERROR("Invalid DTB file passed\n"); 214 return; 215 } 216 217 read_platform_version(dtb); 218 INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor); 219 220 read_platform_config_from_dt(dtb); 221 read_cpuinfo_from_dt(dtb); 222 } 223 224 /* 225 * This function is responsible for handling all SiP calls from the NS world 226 */ 227 uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid, 228 u_register_t x1, 229 u_register_t x2, 230 u_register_t x3, 231 u_register_t x4, 232 void *cookie, 233 void *handle, 234 u_register_t flags) 235 { 236 uint32_t ns; 237 uint64_t index; 238 239 /* Determine which security state this SMC originated from */ 240 ns = is_caller_non_secure(flags); 241 if (!ns) { 242 ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid); 243 SMC_RET1(handle, SMC_UNK); 244 } 245 246 switch (smc_fid) { 247 case SIP_SVC_VERSION: 248 INFO("Platform version requested\n"); 249 SMC_RET3(handle, NULL, platform_version_major, platform_version_minor); 250 251 case SIP_SVC_GET_GIC: 252 SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr()); 253 254 case SIP_SVC_GET_GIC_ITS: 255 SMC_RET2(handle, NULL, gic_its_addr); 256 257 case SIP_SVC_GET_CPU_COUNT: 258 SMC_RET2(handle, NULL, dynamic_platform_info.num_cpus); 259 260 case SIP_SVC_GET_CPU_NODE: 261 index = x1; 262 if (index < PLATFORM_CORE_COUNT) { 263 SMC_RET3(handle, NULL, 264 dynamic_platform_info.cpu[index].nodeid, 265 dynamic_platform_info.cpu[index].mpidr); 266 } else { 267 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM); 268 } 269 270 default: 271 ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid, 272 smc_fid - SIP_FUNCTION); 273 SMC_RET1(handle, SMC_UNK); 274 } 275 } 276 277 int sbsa_sip_smc_setup(void) 278 { 279 return 0; 280 } 281 282 /* Define a runtime service descriptor for fast SMC calls */ 283 DECLARE_RT_SVC( 284 sbsa_sip_svc, 285 OEN_SIP_START, 286 OEN_SIP_END, 287 SMC_TYPE_FAST, 288 sbsa_sip_smc_setup, 289 sbsa_sip_smc_handler 290 ); 291