1 /* 2 * Copyright (c) 2020, Nuvia Inc 3 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <lib/mmio.h> 12 #include <lib/psci/psci.h> 13 #include <plat/common/platform.h> 14 15 #include <platform_def.h> 16 #include "sbsa_private.h" 17 18 #define ADP_STOPPED_APPLICATION_EXIT 0x20026 19 20 /* 21 * Define offset and commands for the fake EC device 22 */ 23 #define SBSA_SECURE_EC_OFFSET 0x50000000 24 25 #define SBSA_SECURE_EC_CMD_SHUTDOWN 0x01 26 #define SBSA_SECURE_EC_CMD_REBOOT 0x02 27 28 /* 29 * The secure entry point to be used on warm reset. 30 */ 31 static unsigned long secure_entrypoint; 32 33 /* Make composite power state parameter till power level 0 */ 34 #if PSCI_EXTENDED_STATE_ID 35 36 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 37 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 38 ((type) << PSTATE_TYPE_SHIFT)) 39 #else 40 #define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 41 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 42 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 43 ((type) << PSTATE_TYPE_SHIFT)) 44 #endif /* PSCI_EXTENDED_STATE_ID */ 45 46 47 #define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 48 (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ 49 qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 50 51 52 53 /* 54 * The table storing the valid idle power states. Ensure that the 55 * array entries are populated in ascending order of state-id to 56 * enable us to use binary search during power state validation. 57 * The table must be terminated by a NULL entry. 58 */ 59 static const unsigned int qemu_pm_idle_states[] = { 60 /* State-id - 0x01 */ 61 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, 62 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), 63 /* State-id - 0x02 */ 64 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, 65 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), 66 /* State-id - 0x22 */ 67 qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, 68 MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), 69 0 70 }; 71 72 /******************************************************************************* 73 * Platform handler called to check the validity of the power state 74 * parameter. The power state parameter has to be a composite power state. 75 ******************************************************************************/ 76 static int qemu_validate_power_state(unsigned int power_state, 77 psci_power_state_t *req_state) 78 { 79 unsigned int state_id; 80 unsigned int i; 81 82 assert(req_state != NULL); 83 84 /* 85 * Currently we are using a linear search for finding the matching 86 * entry in the idle power state array. This can be made a binary 87 * search if the number of entries justifies the additional complexity. 88 */ 89 for (i = 0U; qemu_pm_idle_states[i] != 0U; i++) { 90 if (power_state == qemu_pm_idle_states[i]) { 91 break; 92 } 93 } 94 95 /* Return error if entry not found in the idle state array */ 96 if (qemu_pm_idle_states[i] == 0U) { 97 return PSCI_E_INVALID_PARAMS; 98 } 99 100 i = 0U; 101 state_id = psci_get_pstate_id(power_state); 102 103 /* Parse the State ID and populate the state info parameter */ 104 while (state_id != 0U) { 105 req_state->pwr_domain_state[i++] = state_id & 106 PLAT_LOCAL_PSTATE_MASK; 107 state_id >>= PLAT_LOCAL_PSTATE_WIDTH; 108 } 109 110 return PSCI_E_SUCCESS; 111 } 112 113 /******************************************************************************* 114 * Platform handler called when a CPU is about to enter standby. 115 ******************************************************************************/ 116 static void qemu_cpu_standby(plat_local_state_t cpu_state) 117 { 118 119 assert(cpu_state == PLAT_LOCAL_STATE_RET); 120 121 /* 122 * Enter standby state 123 * dsb is good practice before using wfi to enter low power states 124 */ 125 dsb(); 126 wfi(); 127 } 128 129 /******************************************************************************* 130 * Platform handler called when a power domain is about to be turned on. The 131 * mpidr determines the CPU to be turned on. 132 ******************************************************************************/ 133 static int qemu_pwr_domain_on(u_register_t mpidr) 134 { 135 int pos = plat_core_pos_by_mpidr(mpidr); 136 uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; 137 138 if (pos < 0) { 139 return PSCI_E_INVALID_PARAMS; 140 } 141 142 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; 143 dsb(); 144 sev(); 145 146 return PSCI_E_SUCCESS; 147 } 148 149 /******************************************************************************* 150 * Platform handler called when a power domain is about to be turned off. The 151 * target_state encodes the power state that each level should transition to. 152 ******************************************************************************/ 153 static void qemu_pwr_domain_off(const psci_power_state_t *target_state) 154 { 155 qemu_pwr_gic_off(); 156 } 157 158 void __dead2 plat_secondary_cold_boot_setup(void); 159 160 static void __dead2 161 qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) 162 { 163 disable_mmu_el3(); 164 plat_secondary_cold_boot_setup(); 165 } 166 167 /******************************************************************************* 168 * Platform handler called when a power domain is about to be suspended. The 169 * target_state encodes the power state that each level should transition to. 170 ******************************************************************************/ 171 void qemu_pwr_domain_suspend(const psci_power_state_t *target_state) 172 { 173 assert(false); 174 } 175 176 /******************************************************************************* 177 * Platform handler called when a power domain has just been powered on after 178 * being turned off earlier. The target_state encodes the low power state that 179 * each level has woken up from. 180 ******************************************************************************/ 181 void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) 182 { 183 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == 184 PLAT_LOCAL_STATE_OFF); 185 186 qemu_pwr_gic_on_finish(); 187 } 188 189 /******************************************************************************* 190 * Platform handler called when a power domain has just been powered on after 191 * having been suspended earlier. The target_state encodes the low power state 192 * that each level has woken up from. 193 ******************************************************************************/ 194 void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 195 { 196 assert(false); 197 } 198 199 /******************************************************************************* 200 * Platform handlers to shutdown/reboot the system 201 ******************************************************************************/ 202 static void __dead2 qemu_system_off(void) 203 { 204 mmio_write_32(SBSA_SECURE_EC_OFFSET, SBSA_SECURE_EC_CMD_SHUTDOWN); 205 panic(); 206 } 207 208 static void __dead2 qemu_system_reset(void) 209 { 210 mmio_write_32(SBSA_SECURE_EC_OFFSET, SBSA_SECURE_EC_CMD_REBOOT); 211 panic(); 212 } 213 214 static const plat_psci_ops_t plat_qemu_psci_pm_ops = { 215 .cpu_standby = qemu_cpu_standby, 216 .pwr_domain_on = qemu_pwr_domain_on, 217 .pwr_domain_off = qemu_pwr_domain_off, 218 .pwr_domain_pwr_down = qemu_pwr_domain_pwr_down_wfi, 219 .pwr_domain_suspend = qemu_pwr_domain_suspend, 220 .pwr_domain_on_finish = qemu_pwr_domain_on_finish, 221 .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, 222 .system_off = qemu_system_off, 223 .system_reset = qemu_system_reset, 224 .validate_power_state = qemu_validate_power_state 225 }; 226 227 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 228 const plat_psci_ops_t **psci_ops) 229 { 230 uintptr_t *mailbox = (uintptr_t *)PLAT_QEMU_TRUSTED_MAILBOX_BASE; 231 232 *mailbox = sec_entrypoint; 233 secure_entrypoint = (unsigned long)sec_entrypoint; 234 *psci_ops = &plat_qemu_psci_pm_ops; 235 236 return 0; 237 } 238