1 /* 2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <drivers/arm/gicv3.h> 8 #include <plat/common/platform.h> 9 10 static const interrupt_prop_t qemu_interrupt_props[] = { 11 PLATFORM_G1S_PROPS(INTR_GROUP1S), 12 PLATFORM_G0_PROPS(INTR_GROUP0) 13 }; 14 15 static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 16 17 static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) 18 { 19 return plat_core_pos_by_mpidr(mpidr); 20 } 21 22 static gicv3_driver_data_t sbsa_gic_driver_data = { 23 /* we set those two values for compatibility with older QEMU */ 24 .gicd_base = GICD_BASE, 25 .gicr_base = GICR_BASE, 26 .interrupt_props = qemu_interrupt_props, 27 .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), 28 .rdistif_num = PLATFORM_CORE_COUNT, 29 .rdistif_base_addrs = qemu_rdistif_base_addrs, 30 .mpidr_to_core_pos = qemu_mpidr_to_core_pos 31 }; 32 33 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base) 34 { 35 sbsa_gic_driver_data.gicd_base = gicd_base; 36 sbsa_gic_driver_data.gicr_base = gicr_base; 37 } 38 39 uintptr_t sbsa_get_gicd(void) 40 { 41 return sbsa_gic_driver_data.gicd_base; 42 } 43 44 uintptr_t sbsa_get_gicr(void) 45 { 46 return sbsa_gic_driver_data.gicr_base; 47 } 48 49 void plat_qemu_gic_init(void) 50 { 51 gicv3_driver_init(&sbsa_gic_driver_data); 52 gicv3_distif_init(); 53 gicv3_rdistif_init(plat_my_core_pos()); 54 gicv3_cpuif_enable(plat_my_core_pos()); 55 } 56 57 void qemu_pwr_gic_on_finish(void) 58 { 59 gicv3_rdistif_init(plat_my_core_pos()); 60 gicv3_cpuif_enable(plat_my_core_pos()); 61 } 62 63 void qemu_pwr_gic_off(void) 64 { 65 gicv3_cpuif_disable(plat_my_core_pos()); 66 gicv3_rdistif_off(plat_my_core_pos()); 67 } 68