1*1e67b1b1SMarcin Juszkiewicz /* 2*1e67b1b1SMarcin Juszkiewicz * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. 3*1e67b1b1SMarcin Juszkiewicz * 4*1e67b1b1SMarcin Juszkiewicz * SPDX-License-Identifier: BSD-3-Clause 5*1e67b1b1SMarcin Juszkiewicz */ 6*1e67b1b1SMarcin Juszkiewicz 7*1e67b1b1SMarcin Juszkiewicz #include <drivers/arm/gicv3.h> 8*1e67b1b1SMarcin Juszkiewicz #include <plat/common/platform.h> 9*1e67b1b1SMarcin Juszkiewicz 10*1e67b1b1SMarcin Juszkiewicz static const interrupt_prop_t qemu_interrupt_props[] = { 11*1e67b1b1SMarcin Juszkiewicz PLATFORM_G1S_PROPS(INTR_GROUP1S), 12*1e67b1b1SMarcin Juszkiewicz PLATFORM_G0_PROPS(INTR_GROUP0) 13*1e67b1b1SMarcin Juszkiewicz }; 14*1e67b1b1SMarcin Juszkiewicz 15*1e67b1b1SMarcin Juszkiewicz static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 16*1e67b1b1SMarcin Juszkiewicz 17*1e67b1b1SMarcin Juszkiewicz static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) 18*1e67b1b1SMarcin Juszkiewicz { 19*1e67b1b1SMarcin Juszkiewicz return plat_core_pos_by_mpidr(mpidr); 20*1e67b1b1SMarcin Juszkiewicz } 21*1e67b1b1SMarcin Juszkiewicz 22*1e67b1b1SMarcin Juszkiewicz static gicv3_driver_data_t sbsa_gic_driver_data = { 23*1e67b1b1SMarcin Juszkiewicz /* we set those two values for compatibility with older QEMU */ 24*1e67b1b1SMarcin Juszkiewicz .gicd_base = GICD_BASE, 25*1e67b1b1SMarcin Juszkiewicz .gicr_base = GICR_BASE, 26*1e67b1b1SMarcin Juszkiewicz .interrupt_props = qemu_interrupt_props, 27*1e67b1b1SMarcin Juszkiewicz .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), 28*1e67b1b1SMarcin Juszkiewicz .rdistif_num = PLATFORM_CORE_COUNT, 29*1e67b1b1SMarcin Juszkiewicz .rdistif_base_addrs = qemu_rdistif_base_addrs, 30*1e67b1b1SMarcin Juszkiewicz .mpidr_to_core_pos = qemu_mpidr_to_core_pos 31*1e67b1b1SMarcin Juszkiewicz }; 32*1e67b1b1SMarcin Juszkiewicz 33*1e67b1b1SMarcin Juszkiewicz void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base) 34*1e67b1b1SMarcin Juszkiewicz { 35*1e67b1b1SMarcin Juszkiewicz sbsa_gic_driver_data.gicd_base = gicd_base; 36*1e67b1b1SMarcin Juszkiewicz sbsa_gic_driver_data.gicr_base = gicr_base; 37*1e67b1b1SMarcin Juszkiewicz } 38*1e67b1b1SMarcin Juszkiewicz 39*1e67b1b1SMarcin Juszkiewicz uintptr_t sbsa_get_gicd(void) 40*1e67b1b1SMarcin Juszkiewicz { 41*1e67b1b1SMarcin Juszkiewicz return sbsa_gic_driver_data.gicd_base; 42*1e67b1b1SMarcin Juszkiewicz } 43*1e67b1b1SMarcin Juszkiewicz 44*1e67b1b1SMarcin Juszkiewicz uintptr_t sbsa_get_gicr(void) 45*1e67b1b1SMarcin Juszkiewicz { 46*1e67b1b1SMarcin Juszkiewicz return sbsa_gic_driver_data.gicr_base; 47*1e67b1b1SMarcin Juszkiewicz } 48*1e67b1b1SMarcin Juszkiewicz 49*1e67b1b1SMarcin Juszkiewicz void plat_qemu_gic_init(void) 50*1e67b1b1SMarcin Juszkiewicz { 51*1e67b1b1SMarcin Juszkiewicz gicv3_driver_init(&sbsa_gic_driver_data); 52*1e67b1b1SMarcin Juszkiewicz gicv3_distif_init(); 53*1e67b1b1SMarcin Juszkiewicz gicv3_rdistif_init(plat_my_core_pos()); 54*1e67b1b1SMarcin Juszkiewicz gicv3_cpuif_enable(plat_my_core_pos()); 55*1e67b1b1SMarcin Juszkiewicz } 56*1e67b1b1SMarcin Juszkiewicz 57*1e67b1b1SMarcin Juszkiewicz void qemu_pwr_gic_on_finish(void) 58*1e67b1b1SMarcin Juszkiewicz { 59*1e67b1b1SMarcin Juszkiewicz gicv3_rdistif_init(plat_my_core_pos()); 60*1e67b1b1SMarcin Juszkiewicz gicv3_cpuif_enable(plat_my_core_pos()); 61*1e67b1b1SMarcin Juszkiewicz } 62*1e67b1b1SMarcin Juszkiewicz 63*1e67b1b1SMarcin Juszkiewicz void qemu_pwr_gic_off(void) 64*1e67b1b1SMarcin Juszkiewicz { 65*1e67b1b1SMarcin Juszkiewicz gicv3_cpuif_disable(plat_my_core_pos()); 66*1e67b1b1SMarcin Juszkiewicz gicv3_rdistif_off(plat_my_core_pos()); 67*1e67b1b1SMarcin Juszkiewicz } 68