xref: /rk3399_ARM-atf/plat/qemu/qemu_sbsa/include/qemu_sbsa_pas_def.h (revision b47dddd061e92054c3b2096fc8aa9688bfef68d6)
1 /*
2  * Copyright (c) 2024-2025, Linaro Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 #ifndef QEMU_PAS_DEF_H
7 #define QEMU_PAS_DEF_H
8 
9 #include <lib/gpt_rme/gpt_rme.h>
10 #include "platform_def.h"
11 
12 /*****************************************************************************
13  * PAS regions used to initialize the Granule Protection Table (GPT)
14  ****************************************************************************/
15 
16 /* EL3 SRAM */
17 #define QEMU_PAS_ROOT_BASE	(BL32_MEM_BASE + BL32_MEM_SIZE)
18 #define QEMU_PAS_ROOT_SIZE	(BL_RAM_SIZE - \
19 				 (BL32_MEM_SIZE + RME_GPT_DRAM_SIZE))
20 
21 /* Secure DRAM */
22 #define QEMU_PAS_SEC_BASE	BL32_MEM_BASE /* BL32_SRAM_BASE */
23 #define QEMU_PAS_SEC_SIZE	BL32_MEM_SIZE
24 
25 /* GPTs */
26 #define QEMU_PAS_GPT_BASE	RME_GPT_DRAM_BASE /* PLAT_QEMU_L0_GPT_BASE */
27 #define QEMU_PAS_GPT_SIZE	RME_GPT_DRAM_SIZE
28 
29 /* RMM */
30 #define QEMU_PAS_RMM_BASE	RMM_BASE
31 #define QEMU_PAS_RMM_SIZE	PLAT_QEMU_RMM_SIZE
32 
33 /* Shared area between EL3 and RMM */
34 #define QEMU_PAS_RMM_SHARED_BASE	RMM_SHARED_BASE
35 #define QEMU_PAS_RMM_SHARED_SIZE	RMM_SHARED_SIZE
36 
37 #define QEMU_PAS_ROOT		GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \
38 						       QEMU_PAS_ROOT_SIZE, \
39 						       GPT_GPI_ROOT)
40 
41 #define QEMU_PAS_SECURE		GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \
42 						       QEMU_PAS_SEC_SIZE, \
43 						       GPT_GPI_SECURE)
44 
45 #define QEMU_PAS_GPTS		GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \
46 						       QEMU_PAS_GPT_SIZE, \
47 						       GPT_GPI_ROOT)
48 
49 /*
50  * NS0 base address and size are fetched from the DT at runtime.
51  * See bl31_adjust_pas_regions() for details
52  */
53 #define QEMU_PAS_NS0		GPT_MAP_REGION_GRANULE(0, 0, GPT_GPI_NS)
54 
55 #define QEMU_PAS_REALM		GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \
56 					       QEMU_PAS_RMM_SIZE + \
57 					       QEMU_PAS_RMM_SHARED_SIZE, \
58 					       GPT_GPI_REALM)
59 
60 /* Cover 4TB with L0GTP */
61 #define PLAT_QEMU_GPCCR_PPS	GPCCR_PPS_4TB
62 #define PLAT_QEMU_PPS		SZ_4T
63 
64 /* GPT Configuration options */
65 #define PLATFORM_L0GPTSZ	GPCCR_L0GPTSZ_30BITS
66 
67 #endif /* QEMU_PAS_DEF_H */
68