1acb09373SMathieu Poirier /* 2acb09373SMathieu Poirier * Copyright (c) 2024-2025, Linaro Limited. All rights reserved. 3acb09373SMathieu Poirier * 4acb09373SMathieu Poirier * SPDX-License-Identifier: BSD-3-Clause 5acb09373SMathieu Poirier */ 6acb09373SMathieu Poirier #ifndef QEMU_PAS_DEF_H 7acb09373SMathieu Poirier #define QEMU_PAS_DEF_H 8acb09373SMathieu Poirier 9acb09373SMathieu Poirier #include <lib/gpt_rme/gpt_rme.h> 10acb09373SMathieu Poirier #include "platform_def.h" 11acb09373SMathieu Poirier 12acb09373SMathieu Poirier /***************************************************************************** 13acb09373SMathieu Poirier * PAS regions used to initialize the Granule Protection Table (GPT) 14acb09373SMathieu Poirier ****************************************************************************/ 15acb09373SMathieu Poirier 16acb09373SMathieu Poirier /* EL3 SRAM */ 17acb09373SMathieu Poirier #define QEMU_PAS_ROOT_BASE (BL32_MEM_BASE + BL32_MEM_SIZE) 18acb09373SMathieu Poirier #define QEMU_PAS_ROOT_SIZE (BL_RAM_SIZE - \ 19acb09373SMathieu Poirier (BL32_MEM_SIZE + RME_GPT_DRAM_SIZE)) 20acb09373SMathieu Poirier 21acb09373SMathieu Poirier /* Secure DRAM */ 22acb09373SMathieu Poirier #define QEMU_PAS_SEC_BASE BL32_MEM_BASE /* BL32_SRAM_BASE */ 23acb09373SMathieu Poirier #define QEMU_PAS_SEC_SIZE BL32_MEM_SIZE 24acb09373SMathieu Poirier 25acb09373SMathieu Poirier /* GPTs */ 26acb09373SMathieu Poirier #define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE /* PLAT_QEMU_L0_GPT_BASE */ 27acb09373SMathieu Poirier #define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE 28acb09373SMathieu Poirier 29acb09373SMathieu Poirier /* RMM */ 30acb09373SMathieu Poirier #define QEMU_PAS_RMM_BASE RMM_BASE 31acb09373SMathieu Poirier #define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE 32acb09373SMathieu Poirier 33acb09373SMathieu Poirier /* Shared area between EL3 and RMM */ 34acb09373SMathieu Poirier #define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE 35acb09373SMathieu Poirier #define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE 36acb09373SMathieu Poirier 37acb09373SMathieu Poirier #define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \ 38acb09373SMathieu Poirier QEMU_PAS_ROOT_SIZE, \ 39acb09373SMathieu Poirier GPT_GPI_ROOT) 40acb09373SMathieu Poirier 41acb09373SMathieu Poirier #define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \ 42acb09373SMathieu Poirier QEMU_PAS_SEC_SIZE, \ 43acb09373SMathieu Poirier GPT_GPI_SECURE) 44acb09373SMathieu Poirier 45acb09373SMathieu Poirier #define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \ 46acb09373SMathieu Poirier QEMU_PAS_GPT_SIZE, \ 47acb09373SMathieu Poirier GPT_GPI_ROOT) 48acb09373SMathieu Poirier 49acb09373SMathieu Poirier /* 50acb09373SMathieu Poirier * NS0 base address and size are fetched from the DT at runtime. 51acb09373SMathieu Poirier * See bl31_adjust_pas_regions() for details 52acb09373SMathieu Poirier */ 53acb09373SMathieu Poirier #define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(0, 0, GPT_GPI_NS) 54acb09373SMathieu Poirier 55acb09373SMathieu Poirier #define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \ 56acb09373SMathieu Poirier QEMU_PAS_RMM_SIZE + \ 57acb09373SMathieu Poirier QEMU_PAS_RMM_SHARED_SIZE, \ 58acb09373SMathieu Poirier GPT_GPI_REALM) 59acb09373SMathieu Poirier 60acb09373SMathieu Poirier /* Cover 4TB with L0GTP */ 61*a32a77f9SJean-Philippe Brucker #define PLAT_QEMU_GPCCR_PPS GPCCR_PPS_4TB 62*a32a77f9SJean-Philippe Brucker #define PLAT_QEMU_PPS SZ_4T 63acb09373SMathieu Poirier 64acb09373SMathieu Poirier /* GPT Configuration options */ 65acb09373SMathieu Poirier #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 66acb09373SMathieu Poirier 67acb09373SMathieu Poirier #endif /* QEMU_PAS_DEF_H */ 68