1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. 4 */ 5 6 #ifndef __PLATFORM_DEF_H__ 7 #define __PLATFORM_DEF_H__ 8 9 #include <arch.h> 10 #include <plat/common/common_def.h> 11 #include <tbbr_img_def.h> 12 13 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 14 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 15 16 #define PLATFORM_STACK_SIZE 0x1000 17 18 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 19 #define PLATFORM_CLUSTER_COUNT 2 20 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 21 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 22 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 23 PLATFORM_CLUSTER1_CORE_COUNT) 24 25 #define QEMU_PRIMARY_CPU 0 26 27 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 30 31 #define PLAT_MAX_RET_STATE 1 32 #define PLAT_MAX_OFF_STATE 2 33 34 /* Local power state for power domains in Run state. */ 35 #define PLAT_LOCAL_STATE_RUN 0 36 /* Local power state for retention. Valid only for CPU power domains */ 37 #define PLAT_LOCAL_STATE_RET 1 38 /* 39 * Local power state for OFF/power-down. Valid for CPU and cluster power 40 * domains. 41 */ 42 #define PLAT_LOCAL_STATE_OFF 2 43 44 /* 45 * Macros used to parse state information from State-ID if it is using the 46 * recommended encoding for State-ID. 47 */ 48 #define PLAT_LOCAL_PSTATE_WIDTH 4 49 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 50 51 /* 52 * Some data must be aligned on the biggest cache line size in the platform. 53 * This is known only to the platform as it might have a combination of 54 * integrated and external caches. 55 */ 56 #define CACHE_WRITEBACK_SHIFT 6 57 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 58 59 /* 60 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 61 * and secure DRAM. 62 */ 63 #define SEC_ROM_BASE 0x00000000 64 #define SEC_ROM_SIZE 0x00020000 65 66 #define NS_DRAM0_BASE 0x10000000000ULL 67 #define NS_DRAM0_SIZE 0x00020000000 68 69 #define SEC_SRAM_BASE 0x20000000 70 #define SEC_SRAM_SIZE 0x20000000 71 72 /* 73 * RAD just placeholders, need to be chosen after finalizing mem map 74 */ 75 #define SEC_DRAM_BASE 0x1000 76 #define SEC_DRAM_SIZE 0x1000 77 78 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 79 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 80 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 81 82 /* 83 * ARM-TF lives in SRAM, partition it here 84 */ 85 86 #define SHARED_RAM_BASE SEC_SRAM_BASE 87 #define SHARED_RAM_SIZE 0x00001000 88 89 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 90 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 91 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 92 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 93 PLAT_QEMU_HOLD_ENTRY_SIZE) 94 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 95 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 96 #define PLAT_QEMU_HOLD_STATE_WAIT 0 97 #define PLAT_QEMU_HOLD_STATE_GO 1 98 99 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 100 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 101 102 /* 103 * BL1 specific defines. 104 * 105 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 106 * addresses. 107 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 108 * the current BL1 RW debug size plus a little space for growth. 109 */ 110 #define BL1_RO_BASE SEC_ROM_BASE 111 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 112 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) 113 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 114 115 /* 116 * BL2 specific defines. 117 * 118 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 119 * size plus a little space for growth. 120 */ 121 #define BL2_BASE (BL31_BASE - 0x1D000) 122 #define BL2_LIMIT BL31_BASE 123 124 /* 125 * BL3-1 specific defines. 126 * 127 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 128 * current BL3-1 debug size plus a little space for growth. 129 */ 130 #define BL31_BASE (BL31_LIMIT - 0x20000) 131 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 132 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 133 134 135 /* 136 * BL3-2 specific defines. 137 * 138 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 139 */ 140 #define BL32_SRAM_BASE BL_RAM_BASE 141 #define BL32_SRAM_LIMIT BL31_BASE 142 #define BL32_DRAM_BASE SEC_DRAM_BASE 143 #define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) 144 145 #define BL32_MEM_BASE BL_RAM_BASE 146 #define BL32_MEM_SIZE BL_RAM_SIZE 147 #define BL32_BASE BL32_SRAM_BASE 148 #define BL32_LIMIT BL32_SRAM_LIMIT 149 150 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 151 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 152 153 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42) 154 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42) 155 #define MAX_MMAP_REGIONS 11 156 #define MAX_XLAT_TABLES 10 157 #define MAX_IO_DEVICES 3 158 #define MAX_IO_HANDLES 4 159 160 /* 161 * PL011 related constants 162 */ 163 #define UART0_BASE 0x60000000 164 #define UART1_BASE 0x60030000 165 #define UART0_CLK_IN_HZ 1 166 #define UART1_CLK_IN_HZ 1 167 168 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 169 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 170 171 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 172 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 173 174 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 175 176 #define QEMU_FLASH0_BASE 0x00000000 177 #define QEMU_FLASH0_SIZE 0x10000000 178 #define QEMU_FLASH1_BASE 0x10000000 179 #define QEMU_FLASH1_SIZE 0x10000000 180 181 #define PLAT_QEMU_FIP_BASE 0x00008000 182 #define PLAT_QEMU_FIP_MAX_SIZE 0x00020000 183 184 /* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */ 185 #define DEVICE0_BASE 0x40000000 186 #define DEVICE0_SIZE 0x04080000 187 /* This is map from NORMAL_UART up to SECURE_UART_MM */ 188 #define DEVICE1_BASE 0x60000000 189 #define DEVICE1_SIZE 0x00041000 190 191 /* 192 * GIC related constants 193 * We use GICv3 where CPU Interface registers are not memory mapped 194 */ 195 #define GICD_BASE 0x40060000 196 #define GICR_BASE 0x40080000 197 #define GICC_BASE 0x0 198 199 #define QEMU_IRQ_SEC_SGI_0 8 200 #define QEMU_IRQ_SEC_SGI_1 9 201 #define QEMU_IRQ_SEC_SGI_2 10 202 #define QEMU_IRQ_SEC_SGI_3 11 203 #define QEMU_IRQ_SEC_SGI_4 12 204 #define QEMU_IRQ_SEC_SGI_5 13 205 #define QEMU_IRQ_SEC_SGI_6 14 206 #define QEMU_IRQ_SEC_SGI_7 15 207 208 /****************************************************************************** 209 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 210 * interrupts. 211 *****************************************************************************/ 212 #define PLATFORM_G1S_PROPS(grp) \ 213 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 214 grp, GIC_INTR_CFG_EDGE), \ 215 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 216 grp, GIC_INTR_CFG_EDGE), \ 217 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 218 grp, GIC_INTR_CFG_EDGE), \ 219 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 220 grp, GIC_INTR_CFG_EDGE), \ 221 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 222 grp, GIC_INTR_CFG_EDGE), \ 223 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 224 grp, GIC_INTR_CFG_EDGE), \ 225 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 226 grp, GIC_INTR_CFG_EDGE), \ 227 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 228 grp, GIC_INTR_CFG_EDGE) 229 230 #define PLATFORM_G0_PROPS(grp) 231 232 /* 233 * DT related constants 234 */ 235 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 236 #define PLAT_QEMU_DT_MAX_SIZE 0x10000 237 238 /* 239 * System counter 240 */ 241 #define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) 242 243 #endif /* __PLATFORM_DEF_H__ */ 244