1*6a2426a9SMasahisa Kojima /* SPDX-License-Identifier: BSD-3-Clause 2*6a2426a9SMasahisa Kojima * 3*6a2426a9SMasahisa Kojima * Copyright (c) 2020, Linaro Limited and Contributors. All rights reserved. 4*6a2426a9SMasahisa Kojima */ 5*6a2426a9SMasahisa Kojima 6*6a2426a9SMasahisa Kojima #include <bl31/ehf.h> 7*6a2426a9SMasahisa Kojima #include <lib/xlat_tables/xlat_tables_compat.h> 8*6a2426a9SMasahisa Kojima #include <services/spm_mm_partition.h> 9*6a2426a9SMasahisa Kojima 10*6a2426a9SMasahisa Kojima #include <platform_def.h> 11*6a2426a9SMasahisa Kojima 12*6a2426a9SMasahisa Kojima /* Region equivalent to MAP_DEVICE1 suitable for mapping at EL0 */ 13*6a2426a9SMasahisa Kojima #define MAP_DEVICE1_EL0 MAP_REGION_FLAT(DEVICE1_BASE, \ 14*6a2426a9SMasahisa Kojima DEVICE1_SIZE, \ 15*6a2426a9SMasahisa Kojima MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 16*6a2426a9SMasahisa Kojima 17*6a2426a9SMasahisa Kojima const mmap_region_t plat_qemu_secure_partition_mmap[] = { 18*6a2426a9SMasahisa Kojima MAP_DEVICE1_EL0, /* for the UART */ 19*6a2426a9SMasahisa Kojima QEMU_SP_IMAGE_MMAP, 20*6a2426a9SMasahisa Kojima QEMU_SPM_BUF_EL0_MMAP, 21*6a2426a9SMasahisa Kojima QEMU_SP_IMAGE_NS_BUF_MMAP, 22*6a2426a9SMasahisa Kojima QEMU_SP_IMAGE_RW_MMAP, 23*6a2426a9SMasahisa Kojima {0} 24*6a2426a9SMasahisa Kojima }; 25*6a2426a9SMasahisa Kojima 26*6a2426a9SMasahisa Kojima /* 27*6a2426a9SMasahisa Kojima * Boot information passed to a secure partition during initialisation. 28*6a2426a9SMasahisa Kojima * Linear indices in MP information will be filled at runtime. 29*6a2426a9SMasahisa Kojima */ 30*6a2426a9SMasahisa Kojima static spm_mm_mp_info_t sp_mp_info[] = { 31*6a2426a9SMasahisa Kojima [0] = {0x80000000, 0}, 32*6a2426a9SMasahisa Kojima [1] = {0x80000001, 0}, 33*6a2426a9SMasahisa Kojima [2] = {0x80000002, 0}, 34*6a2426a9SMasahisa Kojima [3] = {0x80000003, 0}, 35*6a2426a9SMasahisa Kojima [4] = {0x80000004, 0}, 36*6a2426a9SMasahisa Kojima [5] = {0x80000005, 0}, 37*6a2426a9SMasahisa Kojima [6] = {0x80000006, 0}, 38*6a2426a9SMasahisa Kojima [7] = {0x80000007, 0} 39*6a2426a9SMasahisa Kojima }; 40*6a2426a9SMasahisa Kojima 41*6a2426a9SMasahisa Kojima const spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = { 42*6a2426a9SMasahisa Kojima .h.type = PARAM_SP_IMAGE_BOOT_INFO, 43*6a2426a9SMasahisa Kojima .h.version = VERSION_1, 44*6a2426a9SMasahisa Kojima .h.size = sizeof(spm_mm_boot_info_t), 45*6a2426a9SMasahisa Kojima .h.attr = 0, 46*6a2426a9SMasahisa Kojima .sp_mem_base = PLAT_QEMU_SP_IMAGE_BASE, 47*6a2426a9SMasahisa Kojima .sp_mem_limit = BL32_LIMIT, 48*6a2426a9SMasahisa Kojima .sp_image_base = PLAT_QEMU_SP_IMAGE_BASE, 49*6a2426a9SMasahisa Kojima .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 50*6a2426a9SMasahisa Kojima .sp_heap_base = PLAT_QEMU_SP_IMAGE_HEAP_BASE, 51*6a2426a9SMasahisa Kojima .sp_ns_comm_buf_base = PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, 52*6a2426a9SMasahisa Kojima .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 53*6a2426a9SMasahisa Kojima .sp_image_size = PLAT_QEMU_SP_IMAGE_SIZE, 54*6a2426a9SMasahisa Kojima .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 55*6a2426a9SMasahisa Kojima .sp_heap_size = PLAT_QEMU_SP_IMAGE_HEAP_SIZE, 56*6a2426a9SMasahisa Kojima .sp_ns_comm_buf_size = PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, 57*6a2426a9SMasahisa Kojima .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 58*6a2426a9SMasahisa Kojima .num_sp_mem_regions = PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS, 59*6a2426a9SMasahisa Kojima .num_cpus = PLATFORM_CORE_COUNT, 60*6a2426a9SMasahisa Kojima .mp_info = sp_mp_info 61*6a2426a9SMasahisa Kojima }; 62*6a2426a9SMasahisa Kojima 63*6a2426a9SMasahisa Kojima /* Enumeration of priority levels on QEMU platforms. */ 64*6a2426a9SMasahisa Kojima ehf_pri_desc_t qemu_exceptions[] = { 65*6a2426a9SMasahisa Kojima EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI) 66*6a2426a9SMasahisa Kojima }; 67*6a2426a9SMasahisa Kojima 68*6a2426a9SMasahisa Kojima /* Plug in QEMU exceptions to Exception Handling Framework. */ 69*6a2426a9SMasahisa Kojima EHF_REGISTER_PRIORITIES(qemu_exceptions, ARRAY_SIZE(qemu_exceptions), 70*6a2426a9SMasahisa Kojima QEMU_PRI_BITS); 71*6a2426a9SMasahisa Kojima 72*6a2426a9SMasahisa Kojima const mmap_region_t *plat_get_secure_partition_mmap(void *cookie) 73*6a2426a9SMasahisa Kojima { 74*6a2426a9SMasahisa Kojima return plat_qemu_secure_partition_mmap; 75*6a2426a9SMasahisa Kojima } 76*6a2426a9SMasahisa Kojima 77*6a2426a9SMasahisa Kojima const spm_mm_boot_info_t * 78*6a2426a9SMasahisa Kojima plat_get_secure_partition_boot_info(void *cookie) 79*6a2426a9SMasahisa Kojima { 80*6a2426a9SMasahisa Kojima return &plat_qemu_secure_partition_boot_info; 81*6a2426a9SMasahisa Kojima } 82