1*301d27d9SRadoslaw Biernacki /* 2*301d27d9SRadoslaw Biernacki * Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved. 3*301d27d9SRadoslaw Biernacki * 4*301d27d9SRadoslaw Biernacki * SPDX-License-Identifier: BSD-3-Clause 5*301d27d9SRadoslaw Biernacki */ 6*301d27d9SRadoslaw Biernacki 7*301d27d9SRadoslaw Biernacki #include <drivers/arm/gicv3.h> 8*301d27d9SRadoslaw Biernacki #include <drivers/arm/gic_common.h> 9*301d27d9SRadoslaw Biernacki #include <platform_def.h> 10*301d27d9SRadoslaw Biernacki #include <plat/common/platform.h> 11*301d27d9SRadoslaw Biernacki 12*301d27d9SRadoslaw Biernacki static const interrupt_prop_t qemu_interrupt_props[] = { 13*301d27d9SRadoslaw Biernacki PLATFORM_G1S_PROPS(INTR_GROUP1S), 14*301d27d9SRadoslaw Biernacki PLATFORM_G0_PROPS(INTR_GROUP0) 15*301d27d9SRadoslaw Biernacki }; 16*301d27d9SRadoslaw Biernacki 17*301d27d9SRadoslaw Biernacki static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 18*301d27d9SRadoslaw Biernacki 19*301d27d9SRadoslaw Biernacki static unsigned int qemu_mpidr_to_core_pos(unsigned long mpidr) 20*301d27d9SRadoslaw Biernacki { 21*301d27d9SRadoslaw Biernacki return (unsigned int)plat_core_pos_by_mpidr(mpidr); 22*301d27d9SRadoslaw Biernacki } 23*301d27d9SRadoslaw Biernacki 24*301d27d9SRadoslaw Biernacki static const gicv3_driver_data_t qemu_gicv3_driver_data = { 25*301d27d9SRadoslaw Biernacki .gicd_base = GICD_BASE, 26*301d27d9SRadoslaw Biernacki .gicr_base = GICR_BASE, 27*301d27d9SRadoslaw Biernacki .interrupt_props = qemu_interrupt_props, 28*301d27d9SRadoslaw Biernacki .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props), 29*301d27d9SRadoslaw Biernacki .rdistif_num = PLATFORM_CORE_COUNT, 30*301d27d9SRadoslaw Biernacki .rdistif_base_addrs = qemu_rdistif_base_addrs, 31*301d27d9SRadoslaw Biernacki .mpidr_to_core_pos = qemu_mpidr_to_core_pos 32*301d27d9SRadoslaw Biernacki }; 33*301d27d9SRadoslaw Biernacki 34*301d27d9SRadoslaw Biernacki void plat_qemu_gic_init(void) 35*301d27d9SRadoslaw Biernacki { 36*301d27d9SRadoslaw Biernacki gicv3_driver_init(&qemu_gicv3_driver_data); 37*301d27d9SRadoslaw Biernacki gicv3_distif_init(); 38*301d27d9SRadoslaw Biernacki gicv3_rdistif_init(plat_my_core_pos()); 39*301d27d9SRadoslaw Biernacki gicv3_cpuif_enable(plat_my_core_pos()); 40*301d27d9SRadoslaw Biernacki } 41*301d27d9SRadoslaw Biernacki 42*301d27d9SRadoslaw Biernacki void qemu_pwr_gic_on_finish(void) 43*301d27d9SRadoslaw Biernacki { 44*301d27d9SRadoslaw Biernacki gicv3_rdistif_init(plat_my_core_pos()); 45*301d27d9SRadoslaw Biernacki gicv3_cpuif_enable(plat_my_core_pos()); 46*301d27d9SRadoslaw Biernacki } 47