1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <drivers/arm/pl061_gpio.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <lib/transfer_list.h> 13 #include <plat/common/platform.h> 14 #if ENABLE_RME 15 #ifdef PLAT_qemu 16 #include <qemu_pas_def.h> 17 #elif PLAT_qemu_sbsa 18 #include <qemu_sbsa_pas_def.h> 19 #endif /* PLAT_qemu */ 20 #endif /* ENABLE_RME */ 21 #ifdef PLAT_qemu_sbsa 22 #include <sbsa_platform.h> 23 #endif 24 25 #include "qemu_private.h" 26 27 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 28 BL31_BASE, \ 29 BL31_END - BL31_BASE, \ 30 MT_MEMORY | MT_RW | EL3_PAS) 31 #define MAP_BL31_RO MAP_REGION_FLAT( \ 32 BL_CODE_BASE, \ 33 BL_CODE_END - BL_CODE_BASE, \ 34 MT_CODE | EL3_PAS), \ 35 MAP_REGION_FLAT( \ 36 BL_RO_DATA_BASE, \ 37 BL_RO_DATA_END \ 38 - BL_RO_DATA_BASE, \ 39 MT_RO_DATA | EL3_PAS) 40 41 #if USE_COHERENT_MEM 42 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 43 BL_COHERENT_RAM_BASE, \ 44 BL_COHERENT_RAM_END \ 45 - BL_COHERENT_RAM_BASE, \ 46 MT_DEVICE | MT_RW | EL3_PAS) 47 #endif 48 49 /* 50 * Placeholder variables for copying the arguments that have been passed to 51 * BL3-1 from BL2. 52 */ 53 static entry_point_info_t bl32_image_ep_info; 54 static entry_point_info_t bl33_image_ep_info; 55 #if ENABLE_RME 56 static entry_point_info_t rmm_image_ep_info; 57 #endif 58 static struct transfer_list_header *bl31_tl; 59 60 /******************************************************************************* 61 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 62 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 63 * they are lost (potentially). This needs to be done before the MMU is 64 * initialized so that the memory layout can be used while creating page 65 * tables. BL2 has flushed this information to memory, so we are guaranteed 66 * to pick up good data. 67 ******************************************************************************/ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 bool is64 = false; 72 uint64_t hval; 73 74 /* Initialize the console to provide early debug support */ 75 qemu_console_init(); 76 77 /* Platform names have to be lowercase. */ 78 #ifdef PLAT_qemu_sbsa 79 sbsa_platform_init(); 80 #endif 81 82 /* 83 * Check params passed from BL2 84 */ 85 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 86 87 assert(params_from_bl2); 88 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 89 assert(params_from_bl2->h.version >= VERSION_2); 90 91 bl_params_node_t *bl_params = params_from_bl2->head; 92 93 /* 94 * Copy BL33, BL32 and RMM (if present), entry point information. 95 * They are stored in Secure RAM, in BL2's address space. 96 */ 97 while (bl_params) { 98 #ifdef __aarch64__ 99 if (bl_params->image_id == BL31_IMAGE_ID && 100 GET_RW(bl_params->ep_info->spsr) == MODE_RW_64) 101 is64 = true; 102 #endif 103 if (bl_params->image_id == BL32_IMAGE_ID) 104 bl32_image_ep_info = *bl_params->ep_info; 105 106 #if ENABLE_RME 107 if (bl_params->image_id == RMM_IMAGE_ID) 108 rmm_image_ep_info = *bl_params->ep_info; 109 #endif 110 111 if (bl_params->image_id == BL33_IMAGE_ID) 112 bl33_image_ep_info = *bl_params->ep_info; 113 114 bl_params = bl_params->next_params_info; 115 } 116 117 if (!bl33_image_ep_info.pc) 118 panic(); 119 #if ENABLE_RME 120 if (!rmm_image_ep_info.pc) 121 panic(); 122 #endif 123 124 if (!TRANSFER_LIST || 125 !transfer_list_check_header((void *)arg3)) 126 return; 127 128 if (is64) 129 hval = TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION); 130 else 131 hval = TRANSFER_LIST_HANDOFF_R1_VALUE(REGISTER_CONVENTION_VERSION); 132 133 if (arg1 != hval) 134 return; 135 136 bl31_tl = (void *)arg3; /* saved TL address from BL2 */ 137 } 138 139 #if ENABLE_RME 140 #if PLAT_qemu 141 /* 142 * The GPT library might modify the gpt regions structure to optimize 143 * the layout, so the array cannot be constant. 144 */ 145 static pas_region_t pas_regions[] = { 146 QEMU_PAS_ROOT, 147 QEMU_PAS_SECURE, 148 QEMU_PAS_GPTS, 149 QEMU_PAS_NS0, 150 QEMU_PAS_REALM, 151 QEMU_PAS_NS1, 152 }; 153 154 static inline void bl31_adjust_pas_regions(void) {} 155 #elif PLAT_qemu_sbsa 156 /* 157 * The GPT library might modify the gpt regions structure to optimize 158 * the layout, so the array cannot be constant. 159 */ 160 static pas_region_t pas_regions[] = { 161 QEMU_PAS_ROOT, 162 QEMU_PAS_SECURE, 163 QEMU_PAS_GPTS, 164 QEMU_PAS_REALM, 165 QEMU_PAS_NS0, 166 }; 167 168 static void bl31_adjust_pas_regions(void) 169 { 170 uint64_t base_addr = 0, total_size = 0; 171 struct platform_memory_data data; 172 uint32_t node; 173 174 /* 175 * The amount of memory supported by the SBSA platform is dynamic 176 * and dependent on user input. Since the configuration of the GPT 177 * needs to reflect the system memory, QEMU_PAS_NS0 needs to be set 178 * based on the information found in the device tree. 179 */ 180 181 for (node = 0; node < sbsa_platform_num_memnodes(); node++) { 182 data = sbsa_platform_memory_node(node); 183 184 if (data.nodeid == 0) { 185 base_addr = data.addr_base; 186 } 187 188 total_size += data.addr_size; 189 } 190 191 /* Index '4' correspond to QEMU_PAS_NS0, see pas_regions[] above */ 192 pas_regions[4].base_pa = base_addr; 193 pas_regions[4].size = total_size; 194 } 195 #endif /* PLAT_qemu */ 196 197 static void bl31_plat_gpt_setup(void) 198 { 199 /* 200 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry 201 * covering 1GB (currently the only supported option), then covering 202 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the 203 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA). 204 */ 205 if (gpt_init_l0_tables(PLATFORM_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE, 206 PLAT_QEMU_L0_GPT_SIZE + 207 PLAT_QEMU_GPT_BITLOCK_SIZE) < 0) { 208 ERROR("gpt_init_l0_tables() failed!\n"); 209 panic(); 210 } 211 212 bl31_adjust_pas_regions(); 213 214 /* Carve out defined PAS ranges. */ 215 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 216 PLAT_QEMU_L1_GPT_BASE, 217 PLAT_QEMU_L1_GPT_SIZE, 218 pas_regions, 219 (unsigned int)(sizeof(pas_regions) / 220 sizeof(pas_region_t))) < 0) { 221 ERROR("gpt_init_pas_l1_tables() failed!\n"); 222 panic(); 223 } 224 225 INFO("Enabling Granule Protection Checks\n"); 226 if (gpt_enable() < 0) { 227 ERROR("gpt_enable() failed!\n"); 228 panic(); 229 } 230 } 231 #endif 232 233 void bl31_plat_arch_setup(void) 234 { 235 const mmap_region_t bl_regions[] = { 236 MAP_BL31_TOTAL, 237 MAP_BL31_RO, 238 #if USE_COHERENT_MEM 239 MAP_BL_COHERENT_RAM, 240 #endif 241 #if ENABLE_RME 242 MAP_GPT_L0_REGION, 243 MAP_GPT_L1_REGION, 244 MAP_RMM_SHARED_MEM, 245 #endif 246 {0} 247 }; 248 249 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 250 251 enable_mmu_el3(0); 252 253 #if ENABLE_RME 254 /* Initialise and enable granule protection after MMU. */ 255 bl31_plat_gpt_setup(); 256 257 /* 258 * Initialise Granule Protection library and enable GPC for the primary 259 * processor. The tables have already been initialized by a previous BL 260 * stage, so there is no need to provide any PAS here. This function 261 * sets up pointers to those tables. 262 */ 263 if (gpt_runtime_init() < 0) { 264 ERROR("gpt_runtime_init() failed!\n"); 265 panic(); 266 } 267 #endif /* ENABLE_RME */ 268 269 } 270 271 static void qemu_gpio_init(void) 272 { 273 #ifdef SECURE_GPIO_BASE 274 pl061_gpio_init(); 275 pl061_gpio_register(SECURE_GPIO_BASE, 0); 276 #endif 277 } 278 279 void bl31_platform_setup(void) 280 { 281 plat_qemu_gic_init(); 282 qemu_gpio_init(); 283 } 284 285 unsigned int plat_get_syscnt_freq2(void) 286 { 287 return read_cntfrq_el0(); 288 } 289 290 /******************************************************************************* 291 * Return a pointer to the 'entry_point_info' structure of the next image 292 * for the security state specified. BL3-3 corresponds to the non-secure 293 * image type while BL3-2 corresponds to the secure image type. A NULL 294 * pointer is returned if the image does not exist. 295 ******************************************************************************/ 296 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 297 { 298 entry_point_info_t *next_image_info; 299 300 assert(sec_state_is_valid(type)); 301 if (type == NON_SECURE) { 302 next_image_info = &bl33_image_ep_info; 303 } 304 #if ENABLE_RME 305 else if (type == REALM) { 306 next_image_info = &rmm_image_ep_info; 307 } 308 #endif 309 else { 310 next_image_info = &bl32_image_ep_info; 311 } 312 313 /* 314 * None of the images on the ARM development platforms can have 0x0 315 * as the entrypoint 316 */ 317 if (next_image_info->pc) 318 return next_image_info; 319 else 320 return NULL; 321 } 322 323 void bl31_plat_runtime_setup(void) 324 { 325 #if TRANSFER_LIST 326 if (bl31_tl) { 327 /* 328 * Relocate the TL from S to NS memory before EL3 exit 329 * to reflect all changes in TL done by BL32 330 */ 331 if (!transfer_list_relocate(bl31_tl, (void *)FW_NS_HANDOFF_BASE, 332 bl31_tl->max_size)) 333 ERROR("Relocate TL to NS memory failed\n"); 334 } 335 #endif 336 337 console_flush(); 338 console_switch_state(CONSOLE_FLAG_RUNTIME); 339 } 340